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From: "Naik, Avadhut" <avadnaik@amd.com>
To: Avadhut Naik <avadhut.naik@amd.com>
Cc: bp@alien8.de, linux-kernel@vger.kernel.org,
	"Žilvinas Žaltiena" <zilvinas@natrix.lt>,
	"Yazen Ghannam" <yazen.ghannam@amd.com>,
	linux-edac@vger.kernel.org
Subject: [PATCH v4] EDAC/amd64: Fix size calculation for Non-Power-of-Two DIMMs
Date: Thu, 22 May 2025 11:12:45 -0500	[thread overview]
Message-ID: <6a0c12e2-08c4-4df1-b1f6-8db8b0029b5f@amd.com> (raw)
In-Reply-To: <20250513192221.784445-1-avadhut.naik@amd.com>

Hi,

Any further feedback on this patch?

-- 
Thanks,
Avadhut Naik

On 5/13/2025 14:20, Avadhut Naik wrote:
> Each Chip-Select (CS) of a Unified Memory Controller (UMC) on AMD's
> modern Zen-based SOCs has an Address Mask and a Secondary Address Mask
> register associated with it. The amd64_edac module logs DIMM sizes on a
> per-UMC per-CS granularity during init using these two registers.
>

  reply	other threads:[~2025-05-22 16:12 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-13 19:20 Avadhut Naik
2025-05-22 16:12 ` Naik, Avadhut [this message]
2025-05-28  9:22 ` Borislav Petkov
2025-05-28 19:38   ` Naik, Avadhut

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