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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: uDqUz4j4SGnK1pOFBnNG7zb2P-9kDc68 X-Proofpoint-GUID: uDqUz4j4SGnK1pOFBnNG7zb2P-9kDc68 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjExMDA4OSBTYWx0ZWRfX5ryZ9pW2u1Kk wf0lKd+OEcWvfcs1dOml69asX3WN94rSmf5KFPfnNUfzq+9ovhUwnUCH85DAOl2oH7zaHwLSubg ZHGUDJPlwy9EaKZl8pfU/KIiExdneWkVrefi6YI9KG42mNSJ6OrLUwEEzTpZoXtkAyUbBnpO10O fOET2LtqP1pQkk2qOd+gt4tfPZYGMSvpbHGEOtai2RomXlBdOh4hd7BTmLGHH3w9+KkqWXz/xkG 6b7V4gHph8Q8eD0l5iHfpUNcyHamaCWhpwa8Ehez++a8pyQuU4Q47/SyJLp0eqpGoZKura0TXTE 32HplZLlnqx/Q7lmwkgXo9SZdqfabhEo5Rtk7DhUShrvPiP70jq9saNBZ9hUH0iM6Os6V9gGXkK rMYQ4quyZalC6+sQpPnw6Q3pISWGeHzA6ckAJ0hPY/4uEcEQwgdCja/UOHMCwseipZvxtgeG9bj Z5MQGDb2VCP90+ix2ew== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjExMDA4OSBTYWx0ZWRfX9jxvZzviY/oZ CpUHCo29t7ANaLwgyhdDLFU9BV2vMAUWT+TSmKokH/jQ47sGvSDCJenWha6dPssgteIJAnipNKx 0MkW6tTApqaPg7TqHSR8T8FmxN+swJU= X-Authority-Analysis: v=2.4 cv=Lf0MLDfi c=1 sm=1 tr=0 ts=6a2a7a22 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=wWqRLLJhWDTYxtXTZgcA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-11_01,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 phishscore=0 clxscore=1015 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606110089 On 6/10/26 1:15 PM, Monish Chunara wrote: > From: Monish Chunara > > Add support for SD card on Glymur SoC and enable the required pinctrl > configurations. > > Co-developed-by: Sachin > Signed-off-by: Sachin Firstname Lastname? > Signed-off-by: Monish Chunara > --- > arch/arm64/boot/dts/qcom/glymur.dtsi | 91 ++++++++++++++++++++++++++++ > 1 file changed, 91 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi > index 20b49af7298e..0989fe39e7ef 100644 > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi > @@ -3927,6 +3927,57 @@ lpass_ag_noc: interconnect@7e40000 { > #interconnect-cells = <2>; > }; > > + sdhc_2: mmc@8804000 { > + compatible = "qcom,glymur-sdhci", "qcom,sdhci-msm-v5"; > + > + reg = <0x0 0x08804000 0x0 0x1000>; nit: Let's drop the \n above > + > + interrupts = , > + ; > + interrupt-names = "hc_irq", > + "pwr_irq"; > + > + clocks = <&gcc GCC_SDCC2_AHB_CLK>, > + <&gcc GCC_SDCC2_APPS_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", > + "core", > + "xo"; > + > + iommus = <&apps_smmu 0xd00 0>; '0x0' for the second value as it's a mask, please > + qcom,dll-config = <0x0007442c>; > + qcom,ddr-config = <0x80040868>; > + > + power-domains = <&rpmhpd RPMHPD_CX>; > + operating-points-v2 = <&sdhc2_opp_table>; > + > + interconnects = <&aggre3_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; > + interconnect-names = "sdhc-ddr", > + "cpu-sdhc"; > + > + bus-width = <4>; > + dma-coherent; > + > + status = "disabled"; > + > + sdhc2_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-100000000 { > + opp-hz = /bits/ 64 <100000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; The SDC doc says this should be 50 MHz> + > + opp-202000000 { > + opp-hz = /bits/ 64 <202000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; And that this should be opp_nom But the clock plan doc has info that corresponds with the content of your patch, please check which one is correct and file a request for fixing the wrong one Konrad