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Wed, 10 Sep 2025 02:07:51 -0700 (PDT) Message-ID: <6a24df18-832c-41b8-8226-5dc5b3c9995d@linaro.org> Date: Wed, 10 Sep 2025 10:07:50 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] perf vendor events arm64 AmpereOneX: Fix typo - should be l1d_cache_access_prefetches To: Ilkka Koskinen Cc: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, John Garry , Will Deacon , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" References: <20250909210120.9823-1-ilkka@os.amperecomputing.com> Content-Language: en-US From: James Clark In-Reply-To: <20250909210120.9823-1-ilkka@os.amperecomputing.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 09/09/2025 10:01 pm, Ilkka Koskinen wrote: > Add missing 'h' to l1d_cache_access_prefetces > > Also fix a couple of typos and use consistent term in brief descriptions > > Fixes: 16438b652b46 ("perf vendor events arm64 AmpereOneX: Add core PMU events and metrics") > Signed-off-by: Ilkka Koskinen > --- > .../arch/arm64/ampere/ampereonex/metrics.json | 10 +++++----- The same typos are in arch/arm64/ampere/ampereone/metrics.json as well. Reviewed-by: James Clark > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json > index 5228f94a793f..6817cac149e0 100644 > --- a/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json > +++ b/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/metrics.json > @@ -113,7 +113,7 @@ > { > "MetricName": "load_store_spec_rate", > "MetricExpr": "LDST_SPEC / INST_SPEC", > - "BriefDescription": "The rate of load or store instructions speculatively executed to overall instructions speclatively executed", > + "BriefDescription": "The rate of load or store instructions speculatively executed to overall instructions speculatively executed", > "MetricGroup": "Operation_Mix", > "ScaleUnit": "100percent of operations" > }, > @@ -132,7 +132,7 @@ > { > "MetricName": "pc_write_spec_rate", > "MetricExpr": "PC_WRITE_SPEC / INST_SPEC", > - "BriefDescription": "The rate of software change of the PC speculatively executed to overall instructions speclatively executed", > + "BriefDescription": "The rate of software change of the PC speculatively executed to overall instructions speculatively executed", > "MetricGroup": "Operation_Mix", > "ScaleUnit": "100percent of operations" > }, > @@ -195,14 +195,14 @@ > { > "MetricName": "stall_frontend_cache_rate", > "MetricExpr": "STALL_FRONTEND_CACHE / CPU_CYCLES", > - "BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and cache miss", > + "BriefDescription": "Proportion of cycles stalled and no operations delivered from frontend and cache miss", > "MetricGroup": "Stall", > "ScaleUnit": "100percent of cycles" > }, > { > "MetricName": "stall_frontend_tlb_rate", > "MetricExpr": "STALL_FRONTEND_TLB / CPU_CYCLES", > - "BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and TLB miss", > + "BriefDescription": "Proportion of cycles stalled and no operations delivered from frontend and TLB miss", > "MetricGroup": "Stall", > "ScaleUnit": "100percent of cycles" > }, > @@ -391,7 +391,7 @@ > "ScaleUnit": "100percent of cache acceses" > }, > { > - "MetricName": "l1d_cache_access_prefetces", > + "MetricName": "l1d_cache_access_prefetches", > "MetricExpr": "L1D_CACHE_PRFM / L1D_CACHE", > "BriefDescription": "L1D cache access - prefetch", > "MetricGroup": "Cache",