From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A2C0C282C2 for ; Wed, 13 Feb 2019 04:26:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CCC79222C1 for ; Wed, 13 Feb 2019 04:26:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="WSkJFxNz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732635AbfBME0B (ORCPT ); Tue, 12 Feb 2019 23:26:01 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:58248 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726530AbfBME0A (ORCPT ); Tue, 12 Feb 2019 23:26:00 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x1D4Ph6f126771; Tue, 12 Feb 2019 22:25:43 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1550031943; bh=ldPf6PLPUt5wJrFZXASWy0gpWvDhqnPw/X7fS0wlK58=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=WSkJFxNzzQuTZIQC0ZgKlXSmKQY9PwoPJtMerive8BSJNg7bpMvM4iokndinubN1D aOrYAGR8rS+aZNtuWhbrMO6zEpFA3+mfzHoM1NZ2JN4rWdmT2Oxbn1Dt+t1HC4Cl79 1f/8wNZLIX8jXwqGugG/zkdzyUgsD+7qc+egbx/c= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x1D4PhJ6053604 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Feb 2019 22:25:43 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Tue, 12 Feb 2019 22:25:43 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Tue, 12 Feb 2019 22:25:43 -0600 Received: from [172.24.190.117] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x1D4Pd3S017352; Tue, 12 Feb 2019 22:25:39 -0600 Subject: Re: [PATCH v5 05/10] dt-bindings: irqchip: Introduce TISCI Interrupt router bindings To: Tony Lindgren CC: , Nishanth Menon , Santosh Shilimkar , Rob Herring , , , Linux ARM Mailing List , , Device Tree Mailing List , Sekhar Nori , Tero Kristo , Peter Ujfalusi References: <20190212074237.2875-1-lokeshvutla@ti.com> <20190212074237.2875-6-lokeshvutla@ti.com> <20190212162247.GK5720@atomide.com> From: Lokesh Vutla Message-ID: <6a274588-0fb6-2ddf-3bcc-f9e4d849ac07@ti.com> Date: Wed, 13 Feb 2019 09:55:22 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <20190212162247.GK5720@atomide.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Tony, On 12/02/19 9:52 PM, Tony Lindgren wrote: > Hi, > > * Lokesh Vutla [190212 07:43]: >> +Example: >> +-------- >> +The following example demonstrates both interrupt router node and the consumer >> +node(main gpio) on the AM654 SoC: >> + >> +main_intr: interrupt-controller0 { >> + compatible = "ti,sci-intr"; >> + interrupt-controller; >> + interrupt-parent = <&gic500>; >> + #interrupt-cells = <4>; >> + ti,sci = <&dmsc>; >> + ti,sci-dst-id = <56>; >> + ti,sci-rm-range-girq = <0x1>; >> +}; > > Can you describe a bit what the "ti,sci-dst-id" is above? > > These IDs seem to be listed at at [0] below, but is it really a property > of the hardware? Or is it some enumeration of SoC devices in the firmware? This is the way that sysfw describes the hardware. In this case it is GIC and it is identified by this ID. Thanks and regards, Lokesh