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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: fPFwy2rkSGnVA7qVW0Mb_U3mNdxU9YMo X-Proofpoint-GUID: fPFwy2rkSGnVA7qVW0Mb_U3mNdxU9YMo X-Authority-Analysis: v=2.4 cv=cb7iaHDM c=1 sm=1 tr=0 ts=69f1829c cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=XvYZRKXU5Z7yJT35SDuk6Q==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=aBoApAjKkzgGVCnEwe8A:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI5MDAzNCBTYWx0ZWRfXx6NoKBPzTLqX KI9/MxZ3oM5Ew//E0/vW5QVrfKPPrZL6gwInyoRjN97AuDkLQNME3Ov3y4dx3vYKcNDowjxof0f ttDyWEyjwZhiGABxEKEr8iwuc1wYyNquvtanXfWROkS06BQxkVLq0hLMC6wfsP3PRcsnyonKkvG M8LbtObg8cXef+2OnqSUzZHKKOxLljUvyD2DKCaaedaglhOCqKkSGNIR9+1Vh8WmWxheTp6J2a5 anPAnD0um3P2Y0vEIOEaUnBxTR+Df8FA3yl6bRwl6zQkrJT/AZbvJ+jsfYVemF7VU2+JB20G7tn 6uOWfZ0yUOpxgoaxIGR2EqyvJULK7kRUy+s6Tda2a/XBz4HCnjMjMtDezr3Lpocp5ho7pHe6qZ5 vmHOqK51nsyMw3IQZy4eArJvLFfX4zPDzU/FxlLm/9iOWaK/qtUkUl8Ax8CQaxdHwVgrbRU/0qd r+FKHnsy5eDQWFJC1CQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-28_05,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 clxscore=1015 impostorscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604290034 On 4/24/2026 5:00 PM, Konrad Dybcio wrote: > On 4/15/26 3:33 PM, Kathiravan Thirumoorthy wrote: >> Add support for the global clock controller found on IPQ9650 SoC. >> >> Signed-off-by: Kathiravan Thirumoorthy >> --- > [...] > >> +static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = { >> + .cmd_rcgr = 0x31004, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcnoc_bfdcd_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + /* >> + * There are no consumers for this source in kernel yet, >> + * (will be added soon), so the clock framework >> + * disables this source. But some of the clocks >> + * initialized by boot loaders uses this source. So we >> + * need to keep this clock ON. Add the >> + * CLK_IGNORE_UNUSED flag so the clock will not be >> + * disabled. Once the consumer in kernel is added, we >> + * can get rid of this flag. >> + */ >> + .flags = CLK_IS_CRITICAL, > I think this clock is normally governed by RPM.. is there RPM/H on this > platform? (doc access still pending..) There is no RPM in this SoC. > If not, what's your plan for this? icc-clk? USB and PCIe clocks uses this source. So once those peripheral supports are landed, we can get rid off this. > > Konrad