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Tue, 10 Nov 2026 07:30:14 -0800 (PST) Received: from [192.168.1.3] ([37.18.141.193]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4983f7801bbsm5510561f8f.5.2026.11.10.07.30.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Nov 2026 07:30:13 -0800 (PST) Message-ID: <6a607357-f613-4a9e-8d38-96ff4f02eec8@linaro.org> Date: Tue, 10 Nov 2026 15:30:12 +0000 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 07/23] coresight: trbe: Publish the session after successful enable To: Leo Yan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org, Suzuki K Poulose , Mike Leach , Alexander Shishkin , Anshuman Khandual , Tamas Petz , Tamas Zsoldos , Suyash Mahar , Amir Ayupov References: <20261016-trbe_enable_disable_irq_handle_refactor-v2-0-3f57cf3199b1@arm.com> <20261016-trbe_enable_disable_irq_handle_refactor-v2-7-3f57cf3199b1@arm.com> Content-Language: en-US From: James Clark In-Reply-To: <20261016-trbe_enable_disable_irq_handle_refactor-v2-7-3f57cf3199b1@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 16/10/2026 17:55, Leo Yan wrote: > arm_trbe_enable() records the session buffer and perf mode before > __arm_trbe_enable() can fail. CoreSight skips the sink disable callback > when sink enable fails, leaving that session state published even though > tracing did not start. > > Install buf->cpudata temporarily for the buffer setup helpers, then call > __arm_trbe_enable() before assigning cpudata->buf and cpudata->mode. > Clear the temporary buffer association if setup fails; the inner helper > still truncates and ends the AUX transaction. > > After successful enable, retain the buffer association across AUX > transactions and clear it in arm_trbe_disable(). > > Signed-off-by: Leo Yan > --- > drivers/hwtracing/coresight/coresight-trbe.c | 15 ++++++++++++--- > 1 file changed, 12 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index 979d0fa84c1c7b448c1ce5cd7a37dff8845795ef..9dfc6bb7afb4c42dfdec643ee7e4f2f193e2b70c 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -69,6 +69,7 @@ struct trbe_buf { > int nr_pages; > void **pages; > bool snapshot; > + /* CPU used to configure this buffer. */ > struct trbe_cpudata *cpudata; > }; > > @@ -137,6 +138,7 @@ struct trbe_save_state { > * @trbe_align - Software alignment used for the TRBPTR_EL1. > * @cpu - CPU this TRBE belongs to. > * @mode - Mode of current operation. (perf/disabled) > + * @buf - Buffer configuration retained for the enabled session. > * @drvdata - TRBE specific drvdata > * @errata - Bit map for the errata on this TRBE. > */ > @@ -1033,17 +1035,24 @@ static int arm_trbe_enable(struct coresight_device *csdev, enum cs_mode mode, > struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev); > struct perf_output_handle *handle = path->handle; > struct trbe_buf *buf = etm_perf_sink_config(handle); > + int ret; > > WARN_ON(cpudata->cpu != smp_processor_id()); > WARN_ON(cpudata->drvdata != drvdata); > if (mode != CS_MODE_PERF) > return -EINVAL; > > - cpudata->buf = buf; > - cpudata->mode = mode; > + /* Buffer helpers need the CPU association while setting up tracing. */ > buf->cpudata = cpudata; > + ret = __arm_trbe_enable(buf, handle); > + if (ret) { > + buf->cpudata = NULL; > + return ret; > + } > > - return __arm_trbe_enable(buf, handle); > + cpudata->buf = buf; > + cpudata->mode = mode; > + return 0; > } > > static int arm_trbe_disable(struct coresight_device *csdev) > Reviewed-by: James Clark