From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6044019BDC; Wed, 24 Apr 2024 22:27:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713997632; cv=none; b=d/wvx9nwIGdxbuJLJEB5aNb2BL4IkWyv6fnjm7JVl9tHD8zIk+VAl9N+665VYFMz68b6H7eOpwM4KMrZqa4iMZbvTF5lO1JJV3zlTf/Y1iPLC/gJNAJuFCLQDLy/as55g39vae0IvWYC965r7Uf11ZU36sMf+iSM2HXiVo+tOTk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713997632; c=relaxed/simple; bh=mr6dI/QUD1Ch9WACeqoktdbI/KcKANVRLuvCXSELSPQ=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=dFA5bkVhsVKvU5lA4wliFfAcpx3xIWniyipsr/rdwIHwSDCqZr470rOJqBGnC24IHsYhQj1nftnHvKVsvF2oPse65u1M3ns0yZ4nFajZQcNgXdTjZEXqLSYYMl1NxPxrJwkU2wG8iVTxoAQGKndWC/FsFMmmbKNjBUEZKs+nbw0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch; spf=pass smtp.mailfrom=lunn.ch; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b=bMRhgFRe; arc=none smtp.client-ip=156.67.10.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lunn.ch Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="bMRhgFRe" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=/U67hF5HIifhfl+FZSrLc2zlLCGyQGz76KtbopmNEG0=; b=bMRhgFRemnmXu6ECTBiBWM1yL6 3JiWbbvywJYzIAbK7mZT8RtiLyxgt3Mlb18/I2KoZzvcsdYoifF6gbmyU5VfY/zoGi6eYpZ6UXemb y0wpqGt0Rm0kSxuwQcdu6TsgtWdkY+Izlz3OfPGQ+vB9GVh35Ao25dqJ9B25ETCpliQs=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1rzl4o-00DtQK-Mk; Thu, 25 Apr 2024 00:26:54 +0200 Date: Thu, 25 Apr 2024 00:26:54 +0200 From: Andrew Lunn To: Matthias Schiffer Cc: Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Fabio Estevam , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux@ew.tq-group.com Subject: Re: [PATCH net v2 1/2] net: dsa: mv88e6xxx: Add support for model-specific pre- and post-reset handlers Message-ID: <6a6959dd-3ab1-4a5c-963b-2146bcbf0b47@lunn.ch> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Apr 23, 2024 at 09:47:48AM +0200, Matthias Schiffer wrote: > Instead of calling mv88e6xxx_g2_eeprom_wait() directly from > mv88e6xxx_hardware_reset(), add configurable pre- and post-reset hard > reset handlers. Initially, the handlers are set to > mv88e6xxx_g2_eeprom_wait() for all families that have get/set_eeprom() > to match the existing behavior. No functional change intended (except > for additional error messages on failure). > > Fixes: 6ccf50d4d474 ("net: dsa: mv88e6xxx: Avoid EEPROM timeout when EEPROM is absent") > Signed-off-by: Matthias Schiffer Reviewed-by: Andrew Lunn Andrew