From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753001AbcGTBhO (ORCPT ); Tue, 19 Jul 2016 21:37:14 -0400 Received: from nat-hk.nvidia.com ([203.18.50.4]:25394 "EHLO hkmmgate102.nvidia.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752348AbcGTBhM (ORCPT ); Tue, 19 Jul 2016 21:37:12 -0400 X-PGP-Universal: processed; by hkpgpgate101.nvidia.com on Tue, 19 Jul 2016 18:37:07 -0700 Subject: Re: [PATCH V3 3/10] Documentation: dt-bindings: firmware: tegra: add bindings of the BPMP To: Rob Herring References: <20160719091723.30919-1-josephl@nvidia.com> <20160719091723.30919-2-josephl@nvidia.com> <20160720012231.GA8522@rob-hp-laptop> CC: Stephen Warren , Thierry Reding , Alexandre Courbot , , , Mark Rutland , Peter De Schrijver , Matthew Longnecker , , Jassi Brar , , Catalin Marinas , Will Deacon , Sivaram Nair From: Joseph Lo Message-ID: <6aafa2af-d9e9-cf7a-6c4f-b7a1f59914bf@nvidia.com> Date: Wed, 20 Jul 2016 09:37:17 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <20160720012231.GA8522@rob-hp-laptop> X-Originating-IP: [10.19.108.111] X-ClientProxiedBy: HKMAIL101.nvidia.com (10.18.16.10) To HKMAIL101.nvidia.com (10.18.16.10) Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/20/2016 09:22 AM, Rob Herring wrote: > On Tue, Jul 19, 2016 at 05:17:23PM +0800, Joseph Lo wrote: >> The BPMP is a specific processor in Tegra chip, which is designed for >> booting process handling and offloading the power management, clock >> management, and reset control tasks from the CPU. The binding document >> defines the resources that would be used by the BPMP firmware driver, >> which can create the interprocessor communication (IPC) between the CPU >> and BPMP. >> >> Signed-off-by: Joseph Lo >> --- >> Changes in V3: >> - s/mmio-ram/mmio-sram/ >> - revise the file path of the reference binding documents and header files >> for more generic viem in different SW projects >> Changes in V2: >> - update the message that the BPMP is clock and reset control provider >> - add tegra186-clock.h and tegra186-reset.h header files >> - revise the description of the required properties >> --- >> .../bindings/firmware/nvidia,tegra186-bpmp.txt | 77 ++ >> include/dt-bindings/clock/tegra186-clock.h | 940 +++++++++++++++++++++ >> include/dt-bindings/reset/tegra186-reset.h | 217 +++++ >> 3 files changed, 1234 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt >> create mode 100644 include/dt-bindings/clock/tegra186-clock.h >> create mode 100644 include/dt-bindings/reset/tegra186-reset.h > > Acked-by: Rob Herring > Rob, Stephen, Thanks for your review. -Joseph