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(host-79-29-83-136.business.telecomitalia.it. [79.29.83.136]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fee915f3dsm57440585e9.1.2026.09.25.05.18.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 05:18:36 -0700 (PDT) Message-ID: <6ab6669c.232cdbff.15fa39.f0d3@mx.google.com> X-Google-Original-Message-ID: Date: Fri, 25 Sep 2026 14:18:34 +0200 From: Christian Marangi To: Andrew Lunn Cc: Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: Re: [RFC PATCH net-next v2] net: pcs: airoha: add support for Airoha AN7583 SoC References: <20260925072712.23419-1-ansuelsmth@gmail.com> <12d6e310-3aa9-45f1-925e-e3c8f2f0efad@lunn.ch> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <12d6e310-3aa9-45f1-925e-e3c8f2f0efad@lunn.ch> On Fri, Sep 25, 2026 at 02:07:52PM +0200, Andrew Lunn wrote: > > +static void an7583_pcs_setup_scu_pcie(struct airoha_pcs_priv *priv, > > + int index, phy_interface_t interface) > > +{ > > + u32 xsi_sel; > > + > > + if (priv->phy) > > + return; > > + > > + switch (interface) { > > + case PHY_INTERFACE_MODE_USXGMII: > > + case PHY_INTERFACE_MODE_10GBASER: > > + default: > > + xsi_sel = AIROHA_SCU_PCIE_XSI1_USXGMII; > > + } > > + > > + regmap_update_bits(priv->scu, AIROHA_SCU_SSTR, > > + AIROHA_SCU_PCIE_XSI1_SEL, > > + xsi_sel); > > I suspect the AI will be here soon. xsi_sel is initially a random > stack value. IF interface is something else, you use that random value > with regmap_update_bits(). > Doesn't default address that case? Anyway PCS for PCIe here is quite special... It does support 2500BASE-X or 10G/USXGMII, but 2500base-x is handled by the USB serdes and 10g is handled by the PCIe serdes and this is internally handled by the SCU reg. This is modelled by the presence of the PHY in DT. - no PHY -> 10g - PHY -> 2500base-x and configuration done by the USB PHY > > static const struct of_device_id airoha_pcs_of_table[] = { > > { .compatible = "airoha,an7581-pcs-eth", .data = &an7581_pcs_eth }, > > { .compatible = "airoha,an7581-pcs-pon", .data = &an7581_pcs_pon }, > > { .compatible = "airoha,an7581-pcs-pcie", .data = &an7581_pcs_pcie }, > > { .compatible = "airoha,an7581-pcs-usb", .data = &an7581_pcs_usb }, > > + { .compatible = "airoha,an7583-pcs-eth", .data = &an7583_pcs_eth }, > > + { .compatible = "airoha,an7583-pcs-pon", .data = &an7583_pcs_pon }, > > + { .compatible = "airoha,an7583-pcs-pcie", .data = &an7583_pcs_pcie }, > > + { .compatible = "airoha,an7583-pcs-usb", .data = &an7583_pcs_usb }, > > Device tree binding update to list these new compatibles? Yes since the AN7581 is still to be merged, I just posted the driver for reference for anyone that is currently using AN7583 and the updated schema will come when it will go out of RFC. > > Andrew -- Ansuel