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([2a01:e0a:999:a3a0:9474:8d75:5115:42cb]) by smtp.gmail.com with ESMTPSA id k14-20020adff5ce000000b00323287186aasm3646419wrp.32.2023.10.04.03.03.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Oct 2023 03:03:41 -0700 (PDT) Message-ID: <6ac16274-3816-4b46-9068-e97af66c815a@rivosinc.com> Date: Wed, 4 Oct 2023 12:03:40 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/7] Add support to handle misaligned accesses in S-mode To: David Laight , Conor Dooley Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Andrew Jones , Evan Green , =?UTF-8?Q?Bj=C3=B6rn_Topel?= , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Ron Minnich , Daniel Maslowski References: <20230926150316.1129648-1-cleger@rivosinc.com> <20230930-patchy-curdle-ef5ee6e1a17c@spud> <8ce6cd97-6d63-4174-a290-40690c81e205@rivosinc.com> Content-Language: en-US From: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/10/2023 10:26, David Laight wrote: > From: Clément Léger >> Sent: 02 October 2023 08:40 >> >> On 30/09/2023 11:23, Conor Dooley wrote: >>> On Tue, Sep 26, 2023 at 05:03:09PM +0200, Clément Léger wrote: >>>> Since commit 61cadb9 ("Provide new description of misaligned load/store >>>> behavior compatible with privileged architecture.") in the RISC-V ISA >>>> manual, it is stated that misaligned load/store might not be supported. >>>> However, the RISC-V kernel uABI describes that misaligned accesses are >>>> supported. > ... > > That it just really horrid. > If the cpu is going to trap misaligned accesses then you want > The compiler generated code (ie packed data) not to generate > misaligned accesses. Hi David, Saying that you support misaligned access does not mean that they are going to be efficient, just that they are supported (in fact, the uABI state that they may perform poorly). The compiler is actually not so stupid and will try to do as much aligned access as possible in what it generates (unless forced by some assembly, cast or whatever that can screw up alignment accesses). This is already the case and it will most probably not change. > So you have to change the kernel uABI. I don't think so. Rule N°1 for kernel development is "Don't break the userspace". So if changing the RISC-V uABI to say "misaligned accesses are not supported", that is unlikely to happen. We stated that misaligned access are supported and thus, they will continue to be supported. > > OTOH if you known that such accesses won't fault and will be > not really slower than aligned accesses then optimised versions > of some functions (like memcpy and checksums) can use misaligned > accesses. Yes, this is selected by HAVE_EFFICIENT_UNALIGNED_ACCESS. On RISC-V, since the specification says nothing about the efficiency of such access, we can't select it like that. Some RISC-V based SoC/CPUs might want to select it manually in their config. In order to support that dynamically and in a generic way, some future work could involve using static keys for such alternatives and enable it based on the speed that was detected. Thanks, Clément > > David > > - > Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK > Registration No: 1397386 (Wales)