From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7E24C433E0 for ; Tue, 19 May 2020 13:39:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B90B1207D8 for ; Tue, 19 May 2020 13:39:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728750AbgESNjp (ORCPT ); Tue, 19 May 2020 09:39:45 -0400 Received: from foss.arm.com ([217.140.110.172]:33070 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726471AbgESNjo (ORCPT ); Tue, 19 May 2020 09:39:44 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E777330E; Tue, 19 May 2020 06:39:43 -0700 (PDT) Received: from [10.37.8.206] (unknown [10.37.8.206]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8D65D3F52E; Tue, 19 May 2020 06:39:42 -0700 (PDT) Subject: Re: [PATCH V4 13/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org References: <1589881254-10082-1-git-send-email-anshuman.khandual@arm.com> <1589881254-10082-14-git-send-email-anshuman.khandual@arm.com> From: Suzuki K Poulose Message-ID: <6ad2dde0-455f-90a6-7b76-eda4fe8d6efe@arm.com> Date: Tue, 19 May 2020 14:44:28 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <1589881254-10082-14-git-send-email-anshuman.khandual@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/19/2020 10:40 AM, Anshuman Khandual wrote: > Enable ETS, TWED, XNX and SPECSEI features bits in ID_AA64MMFR1 register as > per ARM DDI 0487F.a specification. > > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Mark Rutland > Cc: Suzuki K Poulose > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > > Suggested-by: Will Deacon > Signed-off-by: Anshuman Khandual > --- > arch/arm64/include/asm/sysreg.h | 4 ++++ > arch/arm64/kernel/cpufeature.c | 4 ++++ > 2 files changed, 8 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 95fdfc5e9bd0..f9dd2c5ab074 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -734,6 +734,10 @@ > #endif > > /* id_aa64mmfr1 */ > +#define ID_AA64MMFR1_ETS_SHIFT 36 > +#define ID_AA64MMFR1_TWED_SHIFT 32 > +#define ID_AA64MMFR1_XNX_SHIFT 28 > +#define ID_AA64MMFR1_SPECSEI_SHIFT 24 > #define ID_AA64MMFR1_PAN_SHIFT 20 > #define ID_AA64MMFR1_LOR_SHIFT 16 > #define ID_AA64MMFR1_HPD_SHIFT 12 > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 7ce19f97ba73..1f10ff7df705 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -299,6 +299,10 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { > }; > > static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0), SpecSEI must be HIGHER_SAFE, like we did for MMFR4 ? Otherwise looks good to me. Suzuki