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[84.124.213.91]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a359f3e00asm444137735e9.0.2026.10.27.03.26.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Oct 2026 03:26:45 -0700 (PDT) Message-ID: <6ae07c65.e52dcaf0.293af3.e7d5@mx.google.com> Date: Tue, 27 Oct 2026 03:26:45 -0700 (PDT) From: D. Manresa To: antoine.pichot@gmail.com, linux-media@vger.kernel.org Cc: sakari.ailus@linux.intel.com, mchehab@kernel.org, djrscally@gmail.com, dan.scally@ideasonboard.com, hansg@kernel.org, andriy.shevchenko@linux.intel.com, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH 1/7] media: i2c: ov7251: Fix link frequency index In-Reply-To: <20261026111032.88355-2-antoine.pichot@gmail.com> References: <20261026111032.88355-1-antoine.pichot@gmail.com> <20261026111032.88355-2-antoine.pichot@gmail.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 On Mon, Oct 26, 2026 at 08:10:26PM +0900, Antoine Pichot wrote: > Observed on a Surface Book 2, where ipu-bridge lists one link frequency, > 319.2 MHz, which is link_freq[1]: V4L2_CID_LINK_FREQ reads 240000000, > and the pixel rate and PLL registers are off the same way. The diagnosis holds on a Surface Pro 7+ (IPU6 Tiger Lake, 8086:9a19). ipu-bridge gives this machine the same single frequency as yours: IPU_SENSOR_CONFIG("INT347E", 1, 319200000) and unpatched, the sensor reports link_frequency ... value=0 (240000000) pixel_rate ... value=48000000 exactly the mismatch you describe. Applying the patch makes this machine worse, though, and since it carries Cc: stable I think that is worth resolving before it goes in. The fix does not only correct a reported value: it reprograms the PLL and moves the link from 480 to 638.4 Mbps. unpatched v6.19 + this patch link_frequency 0 (240000000) 1 (319200000) pixel_rate 48000000 63840000 PLL1 0x30b1/b3/b4 0x01 / 0x4b / 0x03 0x04 / 0x85 / 0x01 The IPU6 receiver here does not hold that link. 150-frame captures of the 640x480 30 fps mode, counting dropped buffers from v4l2-ctl and csi2-5 error lines from dmesg (including the "callbacks suppressed" lines): unpatched run 1 dropped 23 csi2 errors ~7216 unpatched run 2 dropped 23 csi2 errors 13277 unpatched run 3 dropped 13 csi2 errors 4722 patched run 1 dropped 106 csi2 errors 120788 patched run 3 stalled: 50 frames, then none for 60 s The errors are DPHY fatal error, SOT sync error, inter-frame short/long packet discarded and frame sync error. The frames that do arrive look normal, so this is the link and not the image. Two things to be honest about. This unit is not a clean baseline: even unpatched, mainline already logs thousands of CSI-2 errors per run at 30 fps, and the out-of-tree Surface driver sidesteps the whole area with a vts_boost parameter -- at its production VTS of 3448, 15 fps, I measure zero CSI-2 errors. And the sample is small: three runs each, one unit. What makes me report it anyway is that the one-line difference was consistent in every run, that it introduced hard stalls I never saw unpatched, and that going back to a build with only that line reverted gave 568 consecutive frames with zero CSI-2 errors. One hypothesis tried and failed, so you do not repeat it: the out-of-tree Surface driver notes that the vendor runs the 319.2 MHz PLL with the MIPI divider at 0x01 rather than 0x05. Building this patch with mipi_div changed to 0x01 in the 19_2_mhz_319_2_mhz entry was worse, not better -- 3 frames in about four minutes. So the divider alone is not the missing piece. The vendor path also uses VTS 522, which I did not try. So either ipu-bridge's advertised link frequency is wrong for this SKU, or mainline's 319.2 MHz PLL entry needs more than the index fix to be usable. I have the machine for a few more days and can run whatever would help decide which. The rest of the series tests well here; I have replied to the cover letter with that. D. Manresa (Written with AI assistance, directed and reviewed by me.)