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Mon, 15 Mar 2021 15:19:07 +0000 Received: from [10.25.96.88] (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 15 Mar 2021 15:19:03 +0000 Subject: Re: [PATCH 1/3] ASoC: simple-card-utils: Fix device module clock To: Michael Walle , Mark Brown CC: , , , , , , , , References: <20210309144156.18887-1-michael@walle.cc> <611ed3362dee3b3b7c7a80edfe763fd0@walle.cc> <20210311161558.GG4962@sirena.org.uk> <20210312113544.GB5348@sirena.org.uk> <6ed28bb5330879b1919aced5174f319f@walle.cc> <20210312120456.GD5348@sirena.org.uk> <684332700f8be9f77348a510eb6eba22@walle.cc> <20210312134642.GF5348@sirena.org.uk> <8cdf1cfa971945792b509a687a4de735@walle.cc> From: Sameer Pujar Message-ID: <6af6439c-bdb8-cd0f-635d-069040ba5b65@nvidia.com> Date: Mon, 15 Mar 2021 20:49:00 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <8cdf1cfa971945792b509a687a4de735@walle.cc> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-GB X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 978b7207-e4aa-44bc-8940-08d8e7c5ad41 X-MS-TrafficTypeDiagnostic: BN8PR12MB4771: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kBUABiybkWxBonhgdAOdcpEF3wZg+Pzin3it1O/VdbKnYlExSS6z3j0rOpxoNbRCLmkHFpyW1Ecy0I4y7bVJjqvx31LL5upkkGRK3j9tze7xsShrrn2R1DoJgwLDq5HKkvVtHaJv6g/5aG/B0hMlwWKnAJ8AO20rn7gwnlrvXXzJy5cId3+hWWKEoBqu4nzpcXutabNS9mbJZr3g/lGd/5ntIM87LOLQfO0fG2UDBgRur5oGFqyDFXWcxMiRn4xTlkGBO1gtr06EVhDf3J+GGwhDaTLUkHYq85KOcTVuo7zSSsoHrfzFooIg+529ORObZ6FT4zbHwB0xasLawnWLxw7ghoYg+NIN9AZaC8UgsxTEf6XvC1/yuHx6Vw8HYN0nwYicazh/t3VorNp7RfXN7s8jFmOqC3PP9lRaOHlfWubkygdMK4LVdzFdVN0vK0RzoIMIbUndWs19jSaJOXeGtVT+JCNooarTfdZGnAd4yatXbUF31Cu0/uNM/F0C9iPqUvFHAVVS0C6/VirRMGJ6d+7acE6PKqYQgA6OPkYDjKUE15K4zbOIuDHc2S/bf1sghaXzP0AKTxuxkWwfPwfeTVE6issV/pmzki8c7xKvkqr5MCkGJos7r8tZpFMBG7zBBPjnSaZeAGZdquTTS0kFYom/YE+bTeXiSAd5hsFaqjQOlpVvycZlsx0DeE/wd8I0hdIUo2zYCQ7GE1ZOdDCwlMdyHEcHRs0TYF8/fiSeRf8= X-Forefront-Antispam-Report: CIP:216.228.112.34;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid03.nvidia.com;CAT:NONE;SFS:(4636009)(39860400002)(136003)(396003)(376002)(346002)(36840700001)(46966006)(110136005)(70586007)(36906005)(82310400003)(316002)(186003)(36756003)(16526019)(47076005)(54906003)(16576012)(70206006)(2906002)(86362001)(2616005)(31696002)(8936002)(4326008)(82740400003)(356005)(426003)(5660300002)(336012)(26005)(53546011)(36860700001)(478600001)(31686004)(8676002)(83380400001)(7636003)(34020700004)(43740500002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Mar 2021 15:19:07.3212 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 978b7207-e4aa-44bc-8940-08d8e7c5ad41 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB4771 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/15/2021 5:35 PM, Michael Walle wrote: > External email: Use caution opening links or attachments > > > Am 2021-03-12 14:46, schrieb Mark Brown: >> On Fri, Mar 12, 2021 at 01:30:02PM +0100, Michael Walle wrote: >> >>> The card calls set_sysclk(), which eventually ends up in the codec. >>> The codec therefore, could figure out if it needs to configure the >>> clock or if it can use its internal FLL. >>> Is that what you mean? >> >> Yes. >> >>> But the set_sysclk() of the codec isn't even called, because the >>> card itself already tries to call clk_set_rate() on the Codec's MCLK, >>> which returns with an error [0]. >> >> OK, so I think we need to push this down a level so that the clock >> setting is implemented by the core/CODEC rather than by simple-card, >> with the helpers being something the CODEC can opt out of. > > Sameer, it looks like the proper fix should be to add the clock > support to your codec. I agree that complicated clock relationships should be handled within the codec itself, however MCLK rate setting depends on "mclk-fs" factor and this property is specified as part of simple-card/audio-graph-card codec subnode. Right now codec, in general, does not have a way to know this. The set_sysclk() callback takes rate argument and not the factor. Moreover the same codec is used by other platform vendors too and unless a new DT property is added for codec, runtime MCLK update based on the scaling factor cannot be supported. This would mean that we will be having two methods to specify "mclk-fs" factor, one from simple-card/audio-graph-card and one from respective codec nodes, which does not seem ideal. Also it does not seem consistent with the way we handle MCLK clock based on where it is specified.   a) If specified in simple-card/audio-graph-card, MCLK clock rate/enable/disable updates are allowed.   b) If specified in codec device node, it is not expected to touch the MCLK clock. This patch tried to treat it the same way as (a) does. Advantage of this is, all codec drivers need not explicitly handle MCLK, instead it is done at a central place. The platforms which use specific machine drivers do the same and that is why probably the codec driver patch was never required. It is about just setting MCLK clock as a factor of sample rate, whenever the factor is available. I understand that it is breaking your use case, but I am not sure if the usage of set_sysclk() is consistent. I mean, it takes the "freq" argument. Does it refer to MCLK rate or system-clock (sysclk) rate? MCLK and sysclk are not really the same when codec PLL is involved. So I would like to understand clearly about what "freq" argument means. Also when "mclk-fs" factor is specified, is it related to MCLK or sysclk? My understanding is that it should be strictly viewed as related to MCLK. Does it help if a separate helper is used for audio-graph-card with current change and reverting the simple-card to its previous state? Morimoto-san, does it affect any other users of audio-graph-card? > > I've also looked at other users of "simple-audio-card" and > it looks like they will break too. For example, > - arch/arm64/boot/dts/rockchip/rk3399.dtsi >     If I'm not mistaken, this will try to set the first clock >     of hdmi@ff940000 there, which is "iahb". > - arch/arm/boot/dts/sun8i-a33.dtsi >     There "&ccu CLK_BUS_CODEC" of codec@1c22e00 will be changed > > And it doesn't stop there, it also sets the first clock > of the CPU endpoint, which I guess just works because .set_rate > is a noop for the most clocks which are used there. Yes this is a problem, unfortunately I missed checking some of the simple-card examples. I wonder we should be specifically looking for "mclk" clock here.