From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2866CC433EF for ; Thu, 2 Jun 2022 08:42:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232506AbiFBImh (ORCPT ); Thu, 2 Jun 2022 04:42:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231335AbiFBImd (ORCPT ); Thu, 2 Jun 2022 04:42:33 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C887F38D85; Thu, 2 Jun 2022 01:42:31 -0700 (PDT) X-UUID: 660864278db546d39d1af92858f96de0-20220602 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:bff07ae6-c046-4059-9d2d-ef2339e0fb32,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:2a19b09,CLOUDID:2db4e137-9855-4915-a138-f5705f1f3d02,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: 660864278db546d39d1af92858f96de0-20220602 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1887507329; Thu, 02 Jun 2022 16:42:26 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Thu, 2 Jun 2022 16:42:24 +0800 Received: from [172.21.84.99] (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Thu, 2 Jun 2022 16:42:24 +0800 Subject: Re: [PATCH 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC From: Macpaul Lin To: Yong Wu , Fabien Parent CC: Joerg Roedel , Will Deacon , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , , , , , , Bear Wang , Macross Chen , Kidd-KW Chen , Andy Hsieh , Pablo Sun References: <20220530180328.845692-1-fparent@baylibre.com> <8ac7a6766c635412b408cb5295ddb3da37541140.camel@mediatek.com> <59cedd50-4141-e589-11ae-b8d1a017eb46@mediatek.com> Message-ID: <6b6c4cfc-6f20-0eda-4a0d-31d993341ae8@mediatek.com> Date: Thu, 2 Jun 2022 16:42:24 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <59cedd50-4141-e589-11ae-b8d1a017eb46@mediatek.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6/2/22 4:27 PM, Macpaul Lin wrote: > On 6/2/22 2:18 PM, Yong Wu wrote: >> On Mon, 2022-05-30 at 20:03 +0200, Fabien Parent wrote: >>> Add IOMMU binding documentation for the MT8365 SoC. >>> >>> Signed-off-by: Fabien Parent >>> --- >>>   .../bindings/iommu/mediatek,iommu.yaml        |  2 + >>>   include/dt-bindings/memory/mt8365-larb-port.h | 96 >>> +++++++++++++++++++ >>>   2 files changed, 98 insertions(+) >>>   create mode 100644 include/dt-bindings/memory/mt8365-larb-port.h >> >> [snip...] >> >>> +#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ >>> +#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_ >>> + >>> +#include >>> + >>> +#define M4U_LARB0_ID            0 >>> +#define M4U_LARB1_ID            1 >>> +#define M4U_LARB2_ID            2 >>> +#define M4U_LARB3_ID            3 >>> +#define M4U_LARB4_ID            4 >>> +#define M4U_LARB5_ID            5 >>> +#define M4U_LARB6_ID            6 >>> +#define M4U_LARB7_ID            7 >> >> Remove these. they are no used, right? > > AIOT and customers are using the modules and their related IOMMU modules. > DISP0, VENC, VDEC, ISP (CAMSYS), and APU (as far as I know, which should > be VP6?) were all supported. Dear Yong, How about to replace the following definitions? For example, replace #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(0, 0) to #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID , 0) >> >>> + >>> +/* larb0 */ >>> +#define M4U_PORT_DISP_OVL0        MTK_M4U_ID(0, 0) >>> +#define M4U_PORT_DISP_OVL0_2L    MTK_M4U_ID(0, 1) >> >> [...] >> >>> >>> +/* larb4 */ >>> +#define M4U_PORT_APU_READ        MTK_M4U_ID(0, 0) >>> +#define M4U_PORT_APU_WRITE        MTK_M4U_ID(0, 1) >> >> Please remove these two APU definitions. currently these are not >> supported. > > Kidd, please help to check if APU use these definitions with Yong. > However, I think these are all available to the customers. > > Thanks > Macpaul Lin Thanks Macpaul Lin