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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?FXK4xyK3gqlrUiJxAI2zFg38ZPBwuoY1GL6EISuOW7MgQVU+Kgzzu3EKl5+x?= =?us-ascii?Q?OeMz9ajge3JkWmponwyU8BtprYMIK3JCkykW8QiQPmcHTaGU0FoPZZFLNZMv?= =?us-ascii?Q?zUQBA3xzfEmoNldVR+Egkp9O+bEMbwyXjJKzjQrnN7KnYQcezsZWhhG4kqDa?= =?us-ascii?Q?pR6IM/aRNDjaBbz39nxR6PSytaZLlgcVTKOJnKoC7IYm5m2blOS4XD9S6txa?= =?us-ascii?Q?qpwZMpe2R3tdJRa8mfnIYyTf+N9thWgVDt4kiYcUKuns0GJqmbJ3IAjCrBY+?= =?us-ascii?Q?TYhhxX6HzAhhEJLP8GlnPhvv/Bu7h6RetTPAKhzjvugCi1lJjaA6bdZAbMVl?= =?us-ascii?Q?kEea/9W+jSH2nz/nJYHnbPgG+0hsnBxeRWAvqQ5VM/VCc01gQdQ2+R+i9xk7?= =?us-ascii?Q?KiWI9+3RB1dXkaJXTK4ZJuFqu5tntalK/eQy4g2FlPJst4cL5hr6eoMB+nBU?= =?us-ascii?Q?euKP4J1N+PZlciYVAlPTpHcKXruUcpbdj3d21z4mGp6mHq8nAgQr7AHCR/zz?= =?us-ascii?Q?5dPoLHjZ++1HgRzARZLOdzT+DuFT2/osKm3x0CnaiMnHCRB/csz1Xx+2kdHq?= =?us-ascii?Q?msHtfJAwN3pjqqEo3KX5cLV/OJuqo3ixYfFTPvMp9X/VcX9kdbEmD1SsNqom?= =?us-ascii?Q?bfsvcU2yPgVMRhHTY7aK6879X0lECEMoAJeKRdITUGo/Eho+91BEWKYeqrBm?= =?us-ascii?Q?ZxoXghZSXbN5LciZjjffIoGdShjMxHCcrrWZFTjvQzbeuEhxb9ltYaYmZLD/?= =?us-ascii?Q?CfrRQC0Tzr4SDqxm2+X33J16Jg2jM9JYaB4/ldgaOW3MSTJ0Eu2H+5KsIKA8?= =?us-ascii?Q?3f/80nO/b+NXQyMgA8uZJ/p/WbQT5pE5HjaGVuOaB5DXkwKNG4mmuwkOKCOG?= =?us-ascii?Q?HDu9UHDRInXhm0lcU6eIEfOV5/bYmCvyohF1X5F3T01m+6hTpF72M854nLs4?= =?us-ascii?Q?olbuH8jv0jbaqyJyrVJwUpwUY48z6R+5WeXzUH8Gw82poc1+qPIQEpgmsMhF?= =?us-ascii?Q?y6uVynXHKHvInJjgCjL15Cj/bangJc6iDlnCtuwxGIshGhqlFkMLM/lO/W2+?= =?us-ascii?Q?4s2g7qE5mu6cwGTZlDAwJbv0teGTsESN5Eg9HY3EmYjFq+Nn8aOIwpBL4tU1?= =?us-ascii?Q?1RrU8NVcqroO7b03Vbr9LG8iiWUHNQipxomofDDGFcGU1hS42m7VGUapVLk/?= =?us-ascii?Q?PTix2LR2GsAr1W9NMRgtxtOrKCrc2e/sEZgURLE8bRjK77xtTW07TUIl1YYi?= =?us-ascii?Q?rcoxQC/ehlI2InLjRyreIRBM2P0kVhruFNARnk7Vu+Jld0UQw+xox1wCggQp?= =?us-ascii?Q?cCCp/7kogrwSGzWDLf6qsmhlXQpTZRg/zhuI2wfafgPlCymVa8m5LCUVByx+?= =?us-ascii?Q?b2/nHCEm413tcvn7rx13YF7bLGqPFFWUm1Eet/1liwmjGJ6T8N7OxUCIIG+J?= =?us-ascii?Q?ar1fmRoWzr5OSaxR5X/w213cSXzjIfL0lYmGTafmBPNv0V+POVlwjbE8/E3x?= =?us-ascii?Q?ApYQS8+fi2vpt67Tl1Z3yce8cy0FZrb6Gqo6UYfB6+/9JIPhBIZZMVud8oIz?= =?us-ascii?Q?tMwnYzfR+Kj4BKRmnjvyQPq+rWU8Pxx0usd7PAJB170GGmPmGZ/MY94Vt1Yh?= =?us-ascii?Q?R0gfq6DZmcKOZLKLUnI7fLo=3D?= X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4f8c9647-1d0a-4400-c94d-08db63354f60 X-MS-Exchange-CrossTenant-AuthSource: DM5PR0102MB3590.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2023 06:48:02.0890 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 7oVcGygWHdx8pFQtROALuWvHm/9VBwJfXvyNEBJvzeeTuejGvx3prvmESVDdZtRqkmLqSMkuZC1pg2NcYgbfd73fs7xb3ty7UWJJuQaqCABc1ThofCnsqFlVDrhN1Ebc X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR01MB6970 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Robin, On Thu, 1 Jun 2023, Robin Murphy wrote: > On 2023-06-01 04:01, Ilkka Koskinen wrote: >> Split the 64-bit register accesses if 64-bit access is not supported >> by the PMU. >> >> Signed-off-by: Ilkka Koskinen >> --- >> drivers/perf/arm_cspmu/arm_cspmu.c | 8 ++++++-- >> drivers/perf/arm_cspmu/arm_cspmu.h | 1 + >> 2 files changed, 7 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c >> b/drivers/perf/arm_cspmu/arm_cspmu.c >> index a3f1c410b417..88547a2b73e6 100644 >> --- a/drivers/perf/arm_cspmu/arm_cspmu.c >> +++ b/drivers/perf/arm_cspmu/arm_cspmu.c >> @@ -701,8 +701,12 @@ static void arm_cspmu_write_counter(struct perf_event >> *event, u64 val) >> if (use_64b_counter_reg(cspmu)) { >> offset = counter_offset(sizeof(u64), event->hw.idx); >> - >> - writeq(val, cspmu->base1 + offset); >> + if (!cspmu->impl.split_64bit_access) { > > Could we not just hang this off the 64-bit atomicity property to match the > read path? It doesn't seem like there's much benefit in micro-optimising for > whether the interconnect splits 64-bit accesses into 32-bit bursts vs. just > not accepting them at all. Sure, I was actually wondering if I could use it or if there could be a really weird hw implementation. I'll change it. > >> + writeq(val, cspmu->base1 + offset); >> + } else { >> + writel(lower_32_bits(val), cspmu->base1 + offset); >> + writel(upper_32_bits(val), cspmu->base1 + offset + >> 4); > > lo_hi_writeq() - the header's already included for 32-bit build coverage, so > we may as well put it to use :) Oh, I have missed that function completely. I fix this too. Cheers, Ilkka > Thanks, > Robin. > >> + } >> } else { >> offset = counter_offset(sizeof(u32), event->hw.idx); >> diff --git a/drivers/perf/arm_cspmu/arm_cspmu.h >> b/drivers/perf/arm_cspmu/arm_cspmu.h >> index 51323b175a4a..c0412cf2bd97 100644 >> --- a/drivers/perf/arm_cspmu/arm_cspmu.h >> +++ b/drivers/perf/arm_cspmu/arm_cspmu.h >> @@ -110,6 +110,7 @@ struct arm_cspmu_impl_ops { >> /* Vendor/implementer descriptor. */ >> struct arm_cspmu_impl { >> u32 pmiidr; >> + bool split_64bit_access; >> struct arm_cspmu_impl_ops ops; >> void *ctx; >> }; >