From: Hans Zhang <18255117159@163.com>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: bhelgaas@google.com, helgaas@kernel.org,
ilpo.jarvinen@linux.intel.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 1/1] PCI: of: Relax max-link-speed check to support PCIe Gen5/Gen6
Date: Thu, 18 Dec 2025 20:46:30 +0800 [thread overview]
Message-ID: <6b9c522b-4359-433d-905c-85170ba1c3dc@163.com> (raw)
In-Reply-To: <jwyze44q3dte4ac3ajythb7mxy7sp2hcidugp2kowxubcp6knm@fcixtanjn2ss>
On 2025/12/18 20:44, Manivannan Sadhasivam wrote:
> On Thu, Dec 18, 2025 at 07:56:14PM +0800, Hans Zhang wrote:
>>
>>
>> On 2025/12/18 14:31, Manivannan Sadhasivam wrote:
>>> On Wed, Nov 05, 2025 at 09:47:01PM +0800, Hans Zhang wrote:
>>>> The existing code restricted max-link-speed to values 1~4 (Gen1~Gen4),
>>>> but current SOCs using Synopsys/Cadence IP may require Gen5/Gen6 support.
>>>> While DT binding validation already checks this property, the code-level
>>>> validation in of_pci_get_max_link_speed still lags behind, needing an
>>>> update to accommodate newer PCIe generations.
>>>>
>>>> Hardcoded literals in such validation logic create maintainability
>>>> challenges, as they are difficult to track and update when adding
>>>> support for future PCIe link speeds. To address this, a helper function
>>>> pcie_max_supported_link_speed() is added in drivers/pci/pci.h, which
>>>> calculates the maximum supported link speed generation using existing
>>>> PCIe capability macros (PCI_EXP_LNKCAP_SLS_*). This ensures alignment
>>>> with the kernel's generic PCIe link speed definitions and avoids
>>>> standalone hardcoded values.
>>>>
>>>> The previous hardcoded "4" in the validation check is replaced with a
>>>> call to this helper function, eliminating the need to modify this specific
>>>> code path when extending support for future PCIe generations.
>>>
>>> How can you not modify this function when PCIe 7.0 gets added? It still requires
>>> an update.
>>>
>>> I'd prefer to just drop the check altogether as the callers already have checks
>>> on their own.
>>
>> Hi Mani,
>>
>>
>> Thank you very much for your reply. Do you mean the following modification?
>>
>> diff --git a/drivers/pci/of.c b/drivers/pci/of.c
>> index 3579265f1198..9d3980e425b4 100644
>> --- a/drivers/pci/of.c
>> +++ b/drivers/pci/of.c
>> @@ -890,7 +890,7 @@ int of_pci_get_max_link_speed(struct device_node *node)
>> u32 max_link_speed;
>>
>> if (of_property_read_u32(node, "max-link-speed", &max_link_speed) ||
>> - max_link_speed == 0 || max_link_speed > 4)
>> + max_link_speed == 0)
>> return -EINVAL;
>>
>> return max_link_speed;
>>
>
> Yes! But you could remove the 0 check also.
Hi Mani,
Okay, thank you.
Best regards,
Hans
>
> - Mani
>
prev parent reply other threads:[~2025-12-18 12:46 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-05 13:47 Hans Zhang
2025-12-18 6:31 ` Manivannan Sadhasivam
2025-12-18 11:56 ` Hans Zhang
2025-12-18 12:44 ` Manivannan Sadhasivam
2025-12-18 12:46 ` Hans Zhang [this message]
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