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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=OKsqHCaB c=1 sm=1 tr=0 ts=6995f858 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=IXbkkVN8uJs8XsqYossUiQ==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=ZD5VXX6mDgfP9xSn57MA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE4MDE1MCBTYWx0ZWRfX8TgJpMHXdZla BZwlxpfgaLY/TekmQPl7JDOihjvLS7IG6zrYlJ+FWXWMI06M/aoO72QbCaKeaZcgOAWAIIOKnpN OSLMz9wMhN0ykRYqzii/ed7XKhQnk/skEYPTTaKUf04wrhTA4WPPmO2rpxO+MerAcVOZNDqV7Fn lmXkkOqYVbCszbKr4FIvJ2zvyxkmvnkwVxTEtQuVDiFK/FwSMn49u8LZ25byFAqX0ug1huaqhQt ZpVA3gSsMiG+8EbfEoYTdIHp8R5Wdo7SySF4tsOe5eZWryDcxbI65GS880JqRXyS73xzGjPQTId BHGpXH9xPrUXmrzkj2yXvB4u5LraIHhQdi86YzgbfacrUGk24pUlLl3xUZUe78ixSuY3oTsphe5 KWowShyATw2mWK78n1z6TcYxkOYA6ai/VtUHIvVXmsdtzInVia1hLyYorXqDTfJTmARLJZOacQh Az4HgpQF7vj21WqqxAw== X-Proofpoint-GUID: iFZrC62fev3TaLMlFsxROLV4O69OT7vx X-Proofpoint-ORIG-GUID: iFZrC62fev3TaLMlFsxROLV4O69OT7vx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-18_03,2026-02-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 impostorscore=0 adultscore=0 suspectscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602180150 On 2/17/2026 6:30 PM, Krzysztof Kozlowski wrote: > Glymur is a codename of Qualcomm SoC, not an acronym. > > Signed-off-by: Krzysztof Kozlowski > > --- > > Changes in v2: > Split from previous patchset, because I messed up commands and combined > wrong patches together. > --- > .../devicetree/bindings/clock/qcom,glymur-dispcc.yaml | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml > index 45f027c70e03..9de4ba71f1d9 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml > @@ -4,14 +4,14 @@ > $id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml# > $schema: http://devicetree.org/meta-schemas/core.yaml# > > -title: Qualcomm Display Clock & Reset Controller on GLYMUR > +title: Qualcomm Display Clock & Reset Controller on Glymur SoC > > maintainers: > - Taniya Das > > description: | > Qualcomm display clock control module which supports the clocks, resets and > - power domains for the MDSS instances on GLYMUR SoC. > + power domains for the MDSS instances on Glymur SoC. > > See also: > include/dt-bindings/clock/qcom,dispcc-glymur.h Reviewed-by: Taniya Das -- Thanks, Taniya Das