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Wed, 12 Nov 2025 11:04:13 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG1PEPF000082E4.mail.protection.outlook.com (10.167.240.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9320.13 via Frontend Transport; Wed, 12 Nov 2025 11:04:12 +0000 Received: from [172.16.96.116] (unknown [172.16.96.116]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 23CB440A5BD4; Wed, 12 Nov 2025 19:04:11 +0800 (CST) Message-ID: <6bd16478-4bf9-436a-b862-02d1ebac3d29@cixtech.com> Date: Wed, 12 Nov 2025 19:04:10 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 1/2] PCI: Configure Root Port MPS during host probing To: Shawn Lin , Hans Zhang <18255117159@163.com>, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, helgaas@kernel.org, heiko@sntech.de, mani@kernel.org, yue.wang@Amlogic.com Cc: pali@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, jingoohan1@gmail.com, khilman@baylibre.com, jbrunet@baylibre.com, martin.blumenstingl@googlemail.com, cassel@kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org References: <20251104165125.174168-1-18255117159@163.com> <20251104165125.174168-2-18255117159@163.com> Content-Language: en-US From: Hans Zhang In-Reply-To: Content-Type: text/plain; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 11:04:12.9423 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c57403e5-38e8-4caf-6227-08de21db369f X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E4.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY0PR06MB5756 On 11/12/2025 4:31 PM, Shawn Lin wrote: > EXTERNAL EMAIL > > 在 2025/11/05 星期三 0:51, Hans Zhang 写道: >> Current PCIe initialization logic may leave Root Ports (root bridges) >> operating with non-optimal Maximum Payload Size (MPS) settings. Existing >> code in pci_configure_mps() returns early for devices without an upstream >> bridge (!bridge) which includes Root Ports, so their MPS values remain >> at firmware/hardware defaults. This fails to utilize the controller's >> full >> capabilities, leading to suboptimal data transfer efficiency across the >> PCIe hierarchy. >> >> With this patch, during the host controller probing phase: >> - When PCIe bus tuning is enabled (not PCIE_BUS_TUNE_OFF), and >> - The device is a Root Port without an upstream bridge (!bridge), >> The Root Port's MPS is set to its hardware-supported maximum value >> (128 << dev->pcie_mpss). >> >> Note that this initial maximum MPS setting may be reduced later, during >> downstream device enumeration, if any downstream device does not suppor >> the Root Port's maximum MPS. >> >> This change ensures Root Ports are properly initialized before downstream >> devices negotiate MPS, while maintaining backward compatibility via the >> PCIE_BUS_TUNE_OFF check. >> > > Tested-by: Shawn Lin Hi Shawn, Thank you for your test. Best regards, Hans > >> Suggested-by: Niklas Cassel >> Suggested-by: Manivannan Sadhasivam >> Signed-off-by: Hans Zhang <18255117159@163.com> >> --- >>   drivers/pci/probe.c | 12 ++++++++++++ >>   1 file changed, 12 insertions(+) >> >> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c >> index 0ce98e18b5a8..2459def3af9b 100644 >> --- a/drivers/pci/probe.c >> +++ b/drivers/pci/probe.c >> @@ -2196,6 +2196,18 @@ static void pci_configure_mps(struct pci_dev *dev) >>               return; >>       } >> >> +     /* >> +      * Unless MPS strategy is PCIE_BUS_TUNE_OFF (don't touch MPS at >> all), >> +      * start off by setting Root Ports' MPS to MPSS. This only >> applies to >> +      * Root Ports without an upstream bridge (root bridges), as >> other Root >> +      * Ports will have downstream bridges. Depending on the MPS >> strategy >> +      * and MPSS of downstream devices, the Root Port's MPS may be >> +      * overridden later. >> +      */ >> +     if (!bridge && pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT && >> +         pcie_bus_config != PCIE_BUS_TUNE_OFF) >> +             pcie_set_mps(dev, 128 << dev->pcie_mpss); >> + >>       if (!bridge || !pci_is_pcie(bridge)) >>               return; >> > >