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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id x5sm991191edi.35.2021.01.27.02.04.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Jan 2021 02:04:21 -0800 (PST) Subject: Re: [RESEND PATCH 1/2] KVM: X86: Add support for the emulation of DR6_BUS_LOCK bit To: Xiaoyao Li , Chenyi Qiang , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20210108064924.1677-1-chenyi.qiang@intel.com> <20210108064924.1677-2-chenyi.qiang@intel.com> <5f3089a2-5a5c-a839-9ed9-471c404738a3@intel.com> From: Paolo Bonzini Message-ID: <6bf8fc0d-ad7d-0282-9dcc-695f16af0715@redhat.com> Date: Wed, 27 Jan 2021 11:04:20 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <5f3089a2-5a5c-a839-9ed9-471c404738a3@intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27/01/21 04:41, Xiaoyao Li wrote: > On 1/27/2021 12:31 AM, Paolo Bonzini wrote: >> On 08/01/21 07:49, Chenyi Qiang wrote: >>> To avoid breaking the CPUs without bus lock detection, activate the >>> DR6_BUS_LOCK bit (bit 11) conditionally in DR6_FIXED_1 bits. >>> >>> The set/clear of DR6_BUS_LOCK is similar to the DR6_RTM in DR6 >>> register. The processor clears DR6_BUS_LOCK when bus lock debug >>> exception is generated. (For all other #DB the processor sets this bit >>> to 1.) Software #DB handler should set this bit before returning to the >>> interrupted task. >>> >>> For VM exit caused by debug exception, bit 11 of the exit qualification >>> is set to indicate that a bus lock debug exception condition was >>> detected. The VMM should emulate the exception by clearing bit 11 of the >>> guest DR6. >> >> Please rename DR6_INIT to DR6_ACTIVE_LOW, and then a lot of changes >> become simpler: > > Paolo, > > What do you want to convey with the new name DR6_ACTIVE_LOW? To be > honest, the new name is confusing to me. "Active low" means that the bit is usually 1 and goes to 0 when the condition (such as RTM or bus lock) happens. For almost all those DR6 bits the value is in fact always 1, but if they are defined in the future it will require no code change. Paolo >>> -        dr6 |= DR6_BD | DR6_RTM; >>> +        dr6 |= DR6_BD | DR6_RTM | DR6_BUS_LOCK; >> >> dr6 |= DR6_BD | DR6_ACTIVE_LOW; >> > >