From: Dave Hansen <dave.hansen@intel.com>
To: Fares Mehanna <faresx@amazon.de>,
Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Jarkko Sakkinen <jarkko@kernel.org>,
"Shutemov, Kirill" <kirill.shutemov@intel.com>,
"Williams, Dan J" <dan.j.williams@intel.com>
Cc: x86@kernel.org, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-sgx@vger.kernel.org
Subject: Re: [PATCH] KVM: VMX: pass TME information to guests
Date: Thu, 3 Feb 2022 10:40:50 -0800 [thread overview]
Message-ID: <6c55ac92-0470-07ba-77c0-4701c4ea7ce3@intel.com> (raw)
In-Reply-To: <20220203181432.34911-1-faresx@amazon.de>
On 2/3/22 10:14, Fares Mehanna wrote:
> This will guarantee that hardware supports TME, MSRs are locked, so host can't
> change them and exclusion range is disabled, so TME rules apply on all host
> memory.
But, what's the point? Guests can't trust this information. The host
can lie all it wants about it.
Also, your assumptions about TME rules applying to *all* host memory are
a bit aggressive.
Even if the guest knew for sure that it was reading an MSR directly, it
doesn't mean that any guest memory is actually TME-protected. The
memory could be from a non-TME range like persistent memory. There are
some weasel words in the spec about this:
> Upon activation, all memory (except in TME Exclusion range) attached
> to CPU/SoC is encrypted using AES-XTS 128 bit ephemeral key (platform
> key) that is generated by the CPU on every boot.
The important part here is "attached to the CPU/SoC". I guess they
don't count persistent memory as "attached". This also obviously would
not apply to non-CPU-attached memory that was attached by something like
CXL[1].
The extra fun part of all this is that the architecture doesn't provide
a way to tell if the memory is "attached to the CPU/SoC". That makes it
impossible to get any guarantees out of all this.
In other words, you can't trust the exclusion range in the MSR to be the
*ONLY* non-TME-protected area.
1. https://www.computeexpresslink.org/
prev parent reply other threads:[~2022-02-03 18:41 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-03 18:14 Fares Mehanna
2022-02-03 18:40 ` Dave Hansen [this message]
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