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[83.9.29.77]) by smtp.gmail.com with ESMTPSA id e18-20020ac25472000000b004f4589808cfsm1963021lfn.300.2023.05.29.05.10.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 May 2023 05:10:15 -0700 (PDT) Message-ID: <6c79b99e-cc69-8cd9-c990-5c0373e1f09c@linaro.org> Date: Mon, 29 May 2023 14:10:13 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH 7/7] ARM: dts: qcom: msm8226: Add mdss nodes Content-Language: en-US To: Luca Weiss , ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Andy Gross , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230308-msm8226-mdp-v1-0-679f335d3d5b@z3ntu.xyz> <20230308-msm8226-mdp-v1-7-679f335d3d5b@z3ntu.xyz> From: Konrad Dybcio In-Reply-To: <20230308-msm8226-mdp-v1-7-679f335d3d5b@z3ntu.xyz> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 29.05.2023 11:44, Luca Weiss wrote: > Add the nodes that describe the mdss so that display can work on > MSM8226. > > Signed-off-by: Luca Weiss > --- > arch/arm/boot/dts/qcom-msm8226.dtsi | 118 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 118 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi > index 42acb9ddb8cc..182d6405032f 100644 > --- a/arch/arm/boot/dts/qcom-msm8226.dtsi > +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi > @@ -636,6 +636,124 @@ smd-edge { > label = "lpass"; > }; > }; > + > + mdss: display-subsystem@fd900000 { > + compatible = "qcom,mdss"; > + reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; > + reg-names = "mdss_phys", "vbif_phys"; > + > + power-domains = <&mmcc MDSS_GDSC>; > + > + clocks = <&mmcc MDSS_AHB_CLK>, > + <&mmcc MDSS_AXI_CLK>, > + <&mmcc MDSS_VSYNC_CLK>; > + clock-names = "iface", "bus", "vsync"; One per line, please > + > + interrupts = ; > + > + interrupt-controller; > + #interrupt-cells = <1>; We're not using the irq cell, is that necessary/should that be 0? > + > + status = "disabled"; status should go last > + > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + mdp: display-controller@fd900000 { > + compatible = "qcom,msm8226-mdp5", "qcom,mdp5"; > + reg = <0xfd900100 0x22000>; > + reg-names = "mdp_phys"; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + clocks = <&mmcc MDSS_AHB_CLK>, > + <&mmcc MDSS_AXI_CLK>, > + <&mmcc MDSS_MDP_CLK>, > + <&mmcc MDSS_VSYNC_CLK>; > + clock-names = "iface", "bus", "core", "vsync"; One per line, please > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; Would port { work here? I remember one mdss component's bindings didn't allow it but don't recall which one > + > + port@0 { > + reg = <0>; > + mdp5_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + }; > + }; > + > + dsi0: dsi@fd922800 { > + compatible = "qcom,msm8226-dsi-ctrl", > + "qcom,mdss-dsi-ctrl"; > + reg = <0xfd922800 0x1f8>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; > + assigned-clock-parents = <&dsi_phy0 0>, <&dsi_phy0 1>; One per line, please > + > + clocks = <&mmcc MDSS_MDP_CLK>, > + <&mmcc MDSS_AHB_CLK>, > + <&mmcc MDSS_AXI_CLK>, > + <&mmcc MDSS_BYTE0_CLK>, > + <&mmcc MDSS_PCLK0_CLK>, > + <&mmcc MDSS_ESC0_CLK>, > + <&mmcc MMSS_MISC_AHB_CLK>; > + clock-names = "mdp_core", > + "iface", > + "bus", > + "byte", > + "pixel", > + "core", > + "core_mmss"; > + > + phys = <&dsi_phy0>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&mdp5_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + }; > + }; > + }; > + }; > + > + dsi_phy0: phy@fd922a00 { > + compatible = "qcom,dsi-phy-28nm-8226"; > + reg = <0xfd922a00 0xd4>, > + <0xfd922b00 0x280>, > + <0xfd922d80 0x30>; > + reg-names = "dsi_pll", > + "dsi_phy", > + "dsi_phy_regulator"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; One per line, please Konrad > + clock-names = "iface", "ref"; > + }; > + }; > }; > > timer { >