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Fri, 22 Sep 2023 01:24:28 GMT Received: from [10.239.132.204] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Thu, 21 Sep 2023 18:24:20 -0700 Message-ID: <6c9bee5a-fee6-4c0f-b165-57d40fb41a42@quicinc.com> Date: Fri, 22 Sep 2023 09:24:18 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/5] arm64: dts: qcom: sm4450: Add apps_rsc and cmd_db node To: Konrad Dybcio , , , , , , , , , CC: , , , , , , , , , , , , , , , , , References: <20230920065459.12738-1-quic_tengfan@quicinc.com> <20230920065459.12738-3-quic_tengfan@quicinc.com> <479ce1da-10e5-589d-cb98-e7fef98c5543@linaro.org> From: Tengfei Fan In-Reply-To: <479ce1da-10e5-589d-cb98-e7fef98c5543@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: JGsxiVvRye5xAMH_CplCAfaHbVGQhVcF X-Proofpoint-ORIG-GUID: JGsxiVvRye5xAMH_CplCAfaHbVGQhVcF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-22_01,2023-09-21_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 phishscore=0 suspectscore=0 adultscore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2309220011 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 在 9/20/2023 6:14 PM, Konrad Dybcio 写道: > > > On 9/20/23 08:54, Tengfei Fan wrote: >> From: Ajit Pandey >> >> Add apps_rsc node and cmd_db memory region for sm4450. >> >> Signed-off-by: Ajit Pandey >> Signed-off-by: Tengfei Fan >> --- >>   arch/arm64/boot/dts/qcom/sm4450.dtsi | 35 ++++++++++++++++++++++++++++ >>   1 file changed, 35 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi >> b/arch/arm64/boot/dts/qcom/sm4450.dtsi >> index c4e5b33f5169..3d9d3b5e9510 100644 >> --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi >> @@ -5,6 +5,7 @@ >>   #include >>   #include >> +#include >>   / { >>       interrupt-parent = <&intc>; >> @@ -328,6 +329,18 @@ >>           }; >>       }; >> +    reserved_memory: reserved-memory { >> +        #address-cells = <2>; >> +        #size-cells = <2>; >> +        ranges; >> + >> +        aop_cmd_db_mem: cmd-db@80860000 { >> +            compatible = "qcom,cmd-db"; >> +            reg = <0x0 0x80860000 0x0 0x20000>; >> +            no-map; >> +        }; >> +    }; >> + >>       soc: soc@0 { >>           #address-cells = <2>; >>           #size-cells = <2>; >> @@ -419,6 +432,28 @@ >>                   status = "disabled"; >>               }; >>           }; >> + >> +        apps_rsc: rsc@17a00000 { >> +            compatible = "qcom,rpmh-rsc"; >> +            reg = <0 0x17a00000 0 0x10000>, >> +                  <0 0x17a10000 0 0x10000>, >> +                  <0 0x17a20000 0 0x10000>; > 0x0 for consistency Hi Konrad, Yes, I will update "0" to "0x0" for consistency. > >> +            reg-names = "drv-0", "drv-1", "drv-2"; >> +            interrupts = , >> +                     , >> +                     ; >> +            label = "apps_rsc"; >> +            qcom,tcs-offset = <0xd00>; >> +            qcom,drv-id = <2>; >> +            qcom,tcs-config = , , >> +                      , ; > You haven't addressed Bjorn's comment about the number of > CONTROL_TCSes, are you sure 0 is correct? > > Konrad I got confirm from internal power team, setting CONTROL_TCS with 0 is correct. -- Thx and BRs, Tengfei Fan