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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-672c4d6f63fsm4763703a12.31.2026.04.24.04.30.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Apr 2026 04:30:37 -0700 (PDT) Message-ID: <6ca50a86-0b2a-4eb1-8873-cb80f893174d@oss.qualcomm.com> Date: Fri, 24 Apr 2026 13:30:34 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/5] clk: qcom: add Global Clock controller (GCC) driver for IPQ9650 SoC To: Kathiravan Thirumoorthy , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260415-ipq9650_boot_to_shell-v1-0-b37eb4c3a1d1@oss.qualcomm.com> <20260415-ipq9650_boot_to_shell-v1-2-b37eb4c3a1d1@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260415-ipq9650_boot_to_shell-v1-2-b37eb4c3a1d1@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI0MDExMCBTYWx0ZWRfXw6Zym7zwbN8u 82+Cq2c8FimzvwJQOzjjO1IMhT+6ve43sRDRr7BafhrjjeXpRSJpREoZ82cEzhQscb6EGJMhg50 4/3rOvxNVOdAWZHYY9TTHbkG3we0J1HXgiKGJ0icRmQFFObXvSgLXikuasx1WdQvl+aay4Yjt8a AdxA9kh7eSv7Pa0VUOmVZ4JqJOjWOHS9OKm0idNMmfo9mLzTA8cx7Ub2Oa0dJCc935kqsGR0PM7 p4km+oITyUW/1ipXfHm+JUceDlw0oYgQPzbMIKbhyaSqTXsCXtPDFy7zAp038gQV+LG2Em3SWFn f0849MuKec4ieGoZ202dPTnVh9ytq/bsEyL9Hzk1vhnUCuUZLucMqAv5GXD1yCQCGs77IbLS+rx 1F8UkBWUHzMLXhDB9gUIxfnWmtkbX9rXmPaO53bQTnGS2fEDJrHa9lw7k6qMECWMFxWwyOP4nwj G0I5DGgNlapE/PCnI2g== X-Authority-Analysis: v=2.4 cv=TtnWQjXh c=1 sm=1 tr=0 ts=69eb5460 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=yenN7Bsoyp7keh_6dZ8A:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-ORIG-GUID: ygX-xdZ4Yh5i4aH-_sY5b9C2e6eWymeL X-Proofpoint-GUID: ygX-xdZ4Yh5i4aH-_sY5b9C2e6eWymeL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 clxscore=1015 adultscore=0 spamscore=0 bulkscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604240110 On 4/15/26 3:33 PM, Kathiravan Thirumoorthy wrote: > Add support for the global clock controller found on IPQ9650 SoC. > > Signed-off-by: Kathiravan Thirumoorthy > --- [...] > +static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = { > + .cmd_rcgr = 0x31004, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcnoc_bfdcd_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + /* > + * There are no consumers for this source in kernel yet, > + * (will be added soon), so the clock framework > + * disables this source. But some of the clocks > + * initialized by boot loaders uses this source. So we > + * need to keep this clock ON. Add the > + * CLK_IGNORE_UNUSED flag so the clock will not be > + * disabled. Once the consumer in kernel is added, we > + * can get rid of this flag. > + */ > + .flags = CLK_IS_CRITICAL, I think this clock is normally governed by RPM.. is there RPM/H on this platform? (doc access still pending..) If not, what's your plan for this? icc-clk? Konrad