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Fri, 19 Jul 2024 23:27:33 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.11.0-alpha0-568-g843fbadbe-fm-20240701.003-g843fbadb Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <6cbe8375-c11d-4fbf-8e4f-b15828ac3480@app.fastmail.com> In-Reply-To: <302ca8fb-0185-4872-9d82-d472854e5a43@app.fastmail.com> References: <20240719-smp_i6500-v1-1-8738e67d4802@bootlin.com> <302ca8fb-0185-4872-9d82-d472854e5a43@app.fastmail.com> Date: Sat, 20 Jul 2024 11:27:12 +0800 From: "Jiaxun Yang" To: "Gregory CLEMENT" , "Thomas Bogendoerfer" , "paulburton@kernel.org" Cc: "linux-mips@vger.kernel.org" , linux-kernel@vger.kernel.org, =?UTF-8?Q?Th=C3=A9o_Lebrun?= , "Vladimir Kondratiev" , "Tawfik Bayouk" , "Thomas Petazzoni" Subject: Re: [PATCH] MIPS: SMP-CPS: Fix address for GCR_ACCESS register for I6500 Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82024=E5=B9=B47=E6=9C=8820=E6=97=A5=E4=B8=83=E6=9C=88 =E4=B8=8A=E5= =8D=8811:13=EF=BC=8CJiaxun Yang=E5=86=99=E9=81=93=EF=BC=9A > =E5=9C=A82024=E5=B9=B47=E6=9C=8819=E6=97=A5=E4=B8=83=E6=9C=88 =E4=B8=8B= =E5=8D=8810:14=EF=BC=8CGregory CLEMENT=E5=86=99=E9=81=93=EF=BC=9A >> Unlike most other MIPS CPUs, the I6500 CPUs have different address >> offsets for the Global CSR Access Privilege register. In the "MIPS64 >> I6500 Multiprocessing System Programmer's Guide," it is stated that >> "the Global CSR Access Privilege register is located at offset 0x0120" >> in section 5.4. >> >> However, this is not the case for other MIPS64 CPUs such as the >> P6600. In the "MIPS64=C2=AE P6600 Multiprocessing System Software Use= r's >> Guide," section 6.4.2.6 states that the GCR_ACCESS register has an >> offset of 0x0020. > > Hi Gregory, > > I confirmed this is a CM3 feature rather than CPU core (Samruai) featu= re. Oh I=E2=80=99m not really sure if it=E2=80=99s CM 3.5 only. Let me check this Monday once I can checkout old design database for I64= 00. Hardware resets GCR_ACCESS to the most permissive value so I assume it=E2= =80=99s your bootloader doing wired hacks. Thanks > > Please use CM version to select register region. > (And perhaps Cc stable for this patch?) > > Thanks > - Jiaxun > >> >> This fix allows to use the VP cores in SMP mode. >> >> Based on the work of Vladimir Kondratiev >> >> Fixes: 859aeb1b0dd1 ("MIPS: Probe the I6500 CPU") >> Signed-off-by: Gregory CLEMENT >> --- >> arch/mips/include/asm/mips-cm.h | 4 ++++ >> arch/mips/kernel/smp-cps.c | 5 ++++- >> 2 files changed, 8 insertions(+), 1 deletion(-) >> >> diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/= mips-cm.h >> index 3d9efc802e36..41bf9b3a98fb 100644 >> --- a/arch/mips/include/asm/mips-cm.h >> +++ b/arch/mips/include/asm/mips-cm.h >> @@ -240,6 +240,10 @@ GCR_ACCESSOR_RO(32, 0x0d0, gic_status) >> GCR_ACCESSOR_RO(32, 0x0f0, cpc_status) >> #define CM_GCR_CPC_STATUS_EX BIT(0) >>=20 >> +/* GCR_ACCESS - Controls core/IOCU access to GCRs */ >> +GCR_ACCESSOR_RW(32, 0x120, access_i6500) >> +#define CM_GCR_ACCESS_ACCESSEN GENMASK(7, 0) >> + >> /* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C= =3D1=20 >> */ >> GCR_ACCESSOR_RW(32, 0x130, l2_config) >> #define CM_GCR_L2_CONFIG_BYPASS BIT(20) >> diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c >> index e074138ffd7f..60590890b6da 100644 >> --- a/arch/mips/kernel/smp-cps.c >> +++ b/arch/mips/kernel/smp-cps.c >> @@ -325,7 +325,10 @@ static void boot_core(unsigned int core, unsigne= d=20 >> int vpe_id) >> write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB); >>=20 >> /* Ensure the core can access the GCRs */ >> - set_gcr_access(1 << core); >> + if (current_cpu_type() !=3D CPU_I6500) >> + set_gcr_access(1 << core); >> + else >> + set_gcr_access_i6500(1 << core); >>=20 >> if (mips_cpc_present()) { >> /* Reset the core */ >> >> --- >> base-commit: 9298d51eb3af24f88b211087eb698399f9efa439 >> change-id: 20240719-smp_i6500-8cb233878c41 >> >> Best regards, >> --=20 >> Gregory CLEMENT > > --=20 > - Jiaxun --=20 - Jiaxun