From: Florian Fainelli <f.fainelli@gmail.com>
To: Ansuel Smith <ansuelsmth@gmail.com>, Andrew Lunn <andrew@lunn.ch>,
Vivien Didelot <vivien.didelot@gmail.com>,
Vladimir Oltean <olteanv@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Russell King <linux@armlinux.org.uk>,
netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [net-next PATCH v5 06/14] net: dsa: qca8k: rework rgmii delay logic and scan for cpu port 6
Date: Sun, 10 Oct 2021 19:45:50 -0700 [thread overview]
Message-ID: <6cfe6214-7b78-feca-e7ad-796a37ab369c@gmail.com> (raw)
In-Reply-To: <20211011013024.569-7-ansuelsmth@gmail.com>
On 10/10/2021 6:30 PM, Ansuel Smith wrote:
> Future proof commit. This switch have 2 CPU port and one valid
> configuration is first CPU port set to sgmii and second CPU port set to
> regmii-id. The current implementation detects delay only for CPU port
> zero set to rgmii and doesn't count any delay set in a secondary CPU
> port. Drop the current delay scan function and move it to the sgmii
> parser function to generilize and implicitly add support for secondary
> CPU port set to rgmii-id. Introduce new logic where delay is enabled
> also with internal delay binding declared and rgmii set as PHY mode.
>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
> /* We have 2 CPU port. Check them */
> for (port = 0; port < QCA8K_NUM_PORTS; port++) {
> @@ -1009,14 +948,56 @@ qca8k_parse_port_config(struct qca8k_priv *priv)
>
> dp = dsa_to_port(priv->ds, port);
> port_dn = dp->dn;
> + cpu_port_index++;
Does not this need to be bounded by QCA8K_NUM_CPU_PORTS somehow to be on
the safe side?
--
Florian
next prev parent reply other threads:[~2021-10-11 2:46 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-11 1:30 [net-next PATCH v5 00/14] Multiple improvement for qca8337 switch Ansuel Smith
2021-10-11 1:30 ` [net-next PATCH v5 01/14] net: dsa: qca8k: add mac_power_sel support Ansuel Smith
2021-10-11 1:47 ` Florian Fainelli
2021-10-11 1:30 ` [net-next PATCH v5 02/14] dt-bindings: net: dsa: qca8k: Add SGMII clock phase properties Ansuel Smith
2021-10-11 1:48 ` Florian Fainelli
2021-10-11 1:30 ` [net-next PATCH v5 03/14] net: dsa: qca8k: add support for sgmii falling edge Ansuel Smith
2021-10-11 1:49 ` Florian Fainelli
2021-10-11 1:30 ` [net-next PATCH v5 04/14] dt-bindings: net: dsa: qca8k: Document support for CPU port 6 Ansuel Smith
2021-10-11 1:50 ` Florian Fainelli
2021-10-11 2:02 ` Ansuel Smith
2021-10-11 1:30 ` [net-next PATCH v5 05/14] drivers: net: dsa: qca8k: add support for cpu " Ansuel Smith
2021-10-11 2:01 ` Florian Fainelli
2021-10-11 4:49 ` DENG Qingfang
2021-10-11 1:30 ` [net-next PATCH v5 06/14] net: dsa: qca8k: rework rgmii delay logic and scan " Ansuel Smith
2021-10-11 2:11 ` Florian Fainelli
2021-10-11 2:45 ` Florian Fainelli [this message]
2021-10-11 1:30 ` [net-next PATCH v5 07/14] dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll Ansuel Smith
2021-10-11 1:30 ` [net-next PATCH v5 08/14] net: dsa: qca8k: add explicit SGMII PLL enable Ansuel Smith
2021-10-11 2:46 ` Florian Fainelli
2021-10-11 1:30 ` [net-next PATCH v5 09/14] dt-bindings: net: dsa: qca8k: Document qca,led-open-drain binding Ansuel Smith
2021-10-11 1:30 ` [net-next PATCH v5 10/14] drivers: net: dsa: qca8k: add support for pws config reg Ansuel Smith
2021-10-11 2:48 ` Florian Fainelli
2021-10-11 1:30 ` [net-next PATCH v5 11/14] dt-bindings: net: dsa: qca8k: document support for qca8328 Ansuel Smith
2021-10-11 1:58 ` Florian Fainelli
2021-10-11 1:30 ` [net-next PATCH v5 12/14] drivers: net: dsa: qca8k: add support for QCA8328 Ansuel Smith
2021-10-11 2:42 ` Florian Fainelli
2021-10-11 1:30 ` [net-next PATCH v5 13/14] drivers: net: dsa: qca8k: set internal delay also for sgmii Ansuel Smith
2021-10-11 2:44 ` Florian Fainelli
2021-10-11 1:30 ` [net-next PATCH v5 14/14] drivers: net: dsa: qca8k: move port config to dedicated struct Ansuel Smith
2021-10-11 2:47 ` Florian Fainelli
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