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AJvYcCW4OJawHGbXeG3Ds84aeX6CpRYBk15AZpn7ix9hUb+gaA7LPnKPH+t7Ggve+yzx6rvljon0LJbdKkgIWO8=@vger.kernel.org X-Gm-Message-State: AOJu0YzIC9qgp5qC7KfJm5DdIzvQ6grE7IvymEtx7Flo+KgToiJgyEP5 erDlG0VFz+cqLx2Jtatj68S9wTkcWD4zRB3OU//Y8cyO0LMrSS72gh76rVajUIA= X-Google-Smtp-Source: AGHT+IHoX4497mSUz/yxsu5fS7Yi5t7HC7XwVTZtKpVH7CT0vNJsNQn5cDMNxHVUOof05fQedX8kMw== X-Received: by 2002:a05:600c:4753:b0:431:5632:4497 with SMTP id 5b1f17b1804b1-431bb9d1122mr31382025e9.26.1730291127043; Wed, 30 Oct 2024 05:25:27 -0700 (PDT) Received: from [192.168.0.157] ([79.115.63.43]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431bd918333sm20337295e9.10.2024.10.30.05.25.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Oct 2024 05:25:26 -0700 (PDT) Message-ID: <6d3beeab-c26d-4240-b968-cb13d06d7eae@linaro.org> Date: Wed, 30 Oct 2024 12:25:24 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 11/11] scsi: ufs: exynos: gs101: enable clock gating with hibern8 To: Peter Griffin , alim.akhtar@samsung.com, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, avri.altman@wdc.com, bvanassche@acm.org, krzk@kernel.org Cc: andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, ebiggers@kernel.org References: <20241025131442.112862-1-peter.griffin@linaro.org> <20241025131442.112862-12-peter.griffin@linaro.org> Content-Language: en-US From: Tudor Ambarus In-Reply-To: <20241025131442.112862-12-peter.griffin@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 10/25/24 2:14 PM, Peter Griffin wrote: > Enable clock gating and hibern8 capabilities for gs101. This > leads to a significantly cooler phone when running the upstream > kernel. > > The exynos_ufs_post_hibern8() hook is also updated to remove the > UIC_CMD_DME_HIBER_EXIT code path as this causes a hang on gs101. > > The code path is removed rather than re-factored as no other SoC > in ufs-exynos driver sets UFSHCD_CAP_HIBERN8_WITH_CLK_GATING > capability. Additionally until the previous commit the hibern8 > callbacks were broken anyway as they expected a bool. I think too it's fine to remove uneeded code as it was broken anyway. > > Signed-off-by: Peter Griffin > --- > drivers/ufs/host/ufs-exynos.c | 24 ++++-------------------- > 1 file changed, 4 insertions(+), 20 deletions(-) > > diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c > index 3bbb71f7bae7..7c8195f27bb6 100644 > --- a/drivers/ufs/host/ufs-exynos.c > +++ b/drivers/ufs/host/ufs-exynos.c cut > @@ -1566,26 +1569,7 @@ static void exynos_ufs_post_hibern8(struct ufs_hba *hba, enum uic_cmd_dme cmd) > { cut > + if (cmd == UIC_CMD_DME_HIBER_ENTER) { I verified that the order of operations at hibern8_enter/exit() is sane: Reviewed-by: Tudor Ambarus --- hibern8_notify() gets called in ufshcd_uic_hibern8_enter/exit() exynos_ufs_post_hibern8 disables the clocks for: ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, POST_CHANGE) exynos_ufs_pre_hibern8() enables the clocks for: ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);