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b=ZebhSu7MIws2A4fUKrQzIcjewZ11aAbgVxoiAcnCUClTqlRLfFA6fBCsCR6X9+HqxLDwjcAShLzBtfm1wjg2fxgWHXLNoz15wjayNw0y2KMmUtRNWom8OIrNLG/hL4qTGJ84mfMWeGRVe0apNFrChDWP4AaaQnar/wEFPdeZ13U= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from PH7PR12MB5712.namprd12.prod.outlook.com (2603:10b6:510:1e3::13) by SA1PR12MB8858.namprd12.prod.outlook.com (2603:10b6:806:385::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7741.23; Thu, 4 Jul 2024 08:02:47 +0000 Received: from PH7PR12MB5712.namprd12.prod.outlook.com ([fe80::2efc:dc9f:3ba8:3291]) by PH7PR12MB5712.namprd12.prod.outlook.com ([fe80::2efc:dc9f:3ba8:3291%4]) with mapi id 15.20.7741.027; Thu, 4 Jul 2024 08:02:47 +0000 Message-ID: <6d512a14-ace1-41a3-801e-0beb41425734@amd.com> Date: Thu, 4 Jul 2024 13:32:35 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [Patch v5 12/18] x86: pmu: Improve instruction and branches events verification To: Dapeng Mi Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Xiong Zhang , Zhenyu Wang , Like Xu , Jinrong Liang , Dapeng Mi , ravi.bangoria@amd.com, manali.shukla@amd.com, Sean Christopherson , Paolo Bonzini References: <20240703095712.64202-1-dapeng1.mi@linux.intel.com> <20240703095712.64202-13-dapeng1.mi@linux.intel.com> Content-Language: en-US From: Sandipan Das In-Reply-To: <20240703095712.64202-13-dapeng1.mi@linux.intel.com> Content-Type: text/plain; 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Thus, instructions and branches events can be > verified against a precise count instead of a rough range. > > Signed-off-by: Dapeng Mi > --- > x86/pmu.c | 31 +++++++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/x86/pmu.c b/x86/pmu.c > index d005e376..ffb7b4a4 100644 > --- a/x86/pmu.c > +++ b/x86/pmu.c > @@ -19,6 +19,11 @@ > #define EXPECTED_INSTR 17 > #define EXPECTED_BRNCH 5 > > + > +/* Enable GLOBAL_CTRL + disable GLOBAL_CTRL instructions */ > +#define EXTRA_INSTRNS (3 + 3) > +#define LOOP_INSTRNS (N * 10 + EXTRA_INSTRNS) > +#define LOOP_BRANCHES (N) > #define LOOP_ASM(_wrmsr) \ > _wrmsr "\n\t" \ > "mov %%ecx, %%edi; mov %%ebx, %%ecx;\n\t" \ > @@ -122,6 +127,24 @@ static inline void loop(u64 cntrs) > __precise_loop(cntrs); > } > > +static void adjust_events_range(struct pmu_event *gp_events, > + int instruction_idx, int branch_idx) > +{ > + /* > + * If HW supports GLOBAL_CTRL MSR, enabling and disabling PMCs are > + * moved in __precise_loop(). Thus, instructions and branches events > + * can be verified against a precise count instead of a rough range. > + */ > + if (this_cpu_has_perf_global_ctrl()) { This causes some intermittent failures on AMD processors using PerfMonV2 due to variance in counts. This probably has to do with the way instructions leading to a VM-Entry or VM-Exit are accounted when counting retired instructions and branches. Adding the following change makes all the tests pass again. diff --git a/x86/pmu.c b/x86/pmu.c index 0658a1c1..09a34a3f 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -222,7 +222,7 @@ static void adjust_events_range(struct pmu_event *gp_events, * moved in __precise_loop(). Thus, instructions and branches events * can be verified against a precise count instead of a rough range. */ - if (this_cpu_has_perf_global_ctrl()) { + if (pmu.is_intel && this_cpu_has_perf_global_ctrl()) { /* instructions event */ gp_events[instruction_idx].min = LOOP_INSTRNS; gp_events[instruction_idx].max = LOOP_INSTRNS; > + /* instructions event */ > + gp_events[instruction_idx].min = LOOP_INSTRNS; > + gp_events[instruction_idx].max = LOOP_INSTRNS; > + /* branches event */ > + gp_events[branch_idx].min = LOOP_BRANCHES; > + gp_events[branch_idx].max = LOOP_BRANCHES; > + } > +} > + > volatile uint64_t irq_received; > > static void cnt_overflow(isr_regs_t *regs) > @@ -823,6 +846,9 @@ static void check_invalid_rdpmc_gp(void) > > int main(int ac, char **av) > { > + int instruction_idx; > + int branch_idx; > + > setup_vm(); > handle_irq(PMI_VECTOR, cnt_overflow); > buf = malloc(N*64); > @@ -836,13 +862,18 @@ int main(int ac, char **av) > } > gp_events = (struct pmu_event *)intel_gp_events; > gp_events_size = sizeof(intel_gp_events)/sizeof(intel_gp_events[0]); > + instruction_idx = INTEL_INSTRUCTIONS_IDX; > + branch_idx = INTEL_BRANCHES_IDX; > report_prefix_push("Intel"); > set_ref_cycle_expectations(); > } else { > gp_events_size = sizeof(amd_gp_events)/sizeof(amd_gp_events[0]); > gp_events = (struct pmu_event *)amd_gp_events; > + instruction_idx = AMD_INSTRUCTIONS_IDX; > + branch_idx = AMD_BRANCHES_IDX; > report_prefix_push("AMD"); > } > + adjust_events_range(gp_events, instruction_idx, branch_idx); > > printf("PMU version: %d\n", pmu.version); > printf("GP counters: %d\n", pmu.nr_gp_counters);