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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab7ee6f81fesm3927466b.157.2025.02.11.05.08.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Feb 2025 05:08:34 -0800 (PST) Message-ID: <6d52d3aa-0dab-406d-bf4f-0bace77d46d7@oss.qualcomm.com> Date: Tue, 11 Feb 2025 14:08:32 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8650: add PPI interrupt partitions for the ARM PMUs To: neil.armstrong@linaro.org, Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250207-topic-sm8650-pmu-ppi-partition-v1-0-dd3ba17b3eea@linaro.org> <20250207-topic-sm8650-pmu-ppi-partition-v1-2-dd3ba17b3eea@linaro.org> <6aa71142-3b1d-476f-9c78-1207fbbed3f5@linaro.org> <21f7eb11-bb0d-4e4d-a4b1-780c03fb86d9@oss.qualcomm.com> <36ba4696-1af2-49e7-90bf-f6f559b76fb7@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <36ba4696-1af2-49e7-90bf-f6f559b76fb7@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: 29xGdz0zPSoLjKj3H3qRees6U-b7onIw X-Proofpoint-GUID: 29xGdz0zPSoLjKj3H3qRees6U-b7onIw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-11_05,2025-02-11_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 spamscore=0 clxscore=1015 impostorscore=0 mlxlogscore=985 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502110086 On 11.02.2025 9:02 AM, neil.armstrong@linaro.org wrote: > On 10/02/2025 19:29, Konrad Dybcio wrote: >> On 10.02.2025 4:30 PM, neil.armstrong@linaro.org wrote: >>> On 10/02/2025 16:23, Konrad Dybcio wrote: >>>> On 9.02.2025 3:44 PM, Neil Armstrong wrote: >>>>> On 07/02/2025 21:30, Konrad Dybcio wrote: >>>>>> On 7.02.2025 11:31 AM, Neil Armstrong wrote: >>>>>>> The PMUs shares the same per-cpu (PPI) interrupt, so declare the proper >>>>>>> interrupt partition maps and use the 4th interrupt cell to pass the >>>>>>> partition phandle for each ARM PMU node. >>>>>>> >>>>>>> Signed-off-by: Neil Armstrong >>>>>>> --- >>>>>> >>>>>>> @@ -5309,6 +5309,20 @@ intc: interrupt-controller@17100000 { >>>>>>>                 #size-cells = <2>; >>>>>>>                 ranges; >>>>>>>     +            ppi-partitions { >>>>>>> +                ppi_cluster0: interrupt-partition-0 { >>>>>>> +                    affinity = <&cpu0 &cpu1>; >>>>>>> +                }; >>>>>>> + >>>>>>> +                ppi_cluster1: interrupt-partition-1 { >>>>>>> +                    affinity = <&cpu2 &cpu3 &cpu4 &cpu5 &cpu6>; >>>>>>> +                }; >>>>>>> + >>>>>>> +                ppi_cluster2: interrupt-partition-2 { >>>>>>> +                    affinity = <&cpu7>; >>>>>>> +                }; >>>>>> >>>>>> I'm not sure this is accurate. >>>>>> >>>>>> I *think* it's cores 0-1 and 2-7, but I can't find a concrete answer >>>>> >>>>> Core 7 is a Cortex-X4, and has a dedicated PMU node, look at the cpu compatibles. >>>> >>>> Look at what these compatibles do in code. Nothing special for the X. >>> >>> So you suggest to revert Rob's change ? >>> >>> https://lore.kernel.org/all/20240417204247.3216703-1-robh@kernel.org/ >>> >>> So what I understood is that yes the code is the same, but the perf >>> attributes are not necessarily the same between heterogeneous cores, >>> so each instance here would load the attributes for each core type >>> correctly instead of only using the ones from the first core >>> >>> Again, other SoCs uses this same scheme so I wonder what's the issue here ? >> >> So I'm a little confused here. Is this partitioning scheme only describing >> a set of same-kind cores to Linux so that the PMU interrupts only arrive at >> one PMU device? Or does it reflect some actual physical topology of clusters >> and how they're connected to the GIC? >> >> If the former, I have no issues with this version of the patch. > > The former, we simply partition the PPI interrupt for each device node, it > has obviously something to do with the topology, but the goal is not to describe > the topology. Ok, good Reviewed-by: Konrad Dybcio Konrad