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Fri, 29 May 2026 02:23:36 -0700 (PDT) X-Received: by 2002:a05:6a00:4f8e:b0:81f:31c3:2e34 with SMTP id d2e1a72fcca58-84212b83c1cmr2358688b3a.25.1780046615661; Fri, 29 May 2026 02:23:35 -0700 (PDT) Received: from [192.168.1.2] ([117.192.250.176]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84214affe29sm1240298b3a.3.2026.05.29.02.23.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 May 2026 02:23:34 -0700 (PDT) Message-ID: <6d5fa33f-449e-4f22-b0d1-60a3a21a9907@oss.qualcomm.com> Date: Fri, 29 May 2026 14:53:29 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/5] dt-bindings: clock: qcom: Add Qualcomm Shikra Display clock controller To: Dmitry Baryshkov Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Loic Poulain , Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260528-shikra-dispcc-gpucc-v2-0-953f246a0fbb@oss.qualcomm.com> <20260528-shikra-dispcc-gpucc-v2-2-953f246a0fbb@oss.qualcomm.com> <5nghgd3lt6vyewd3a7l4kahlxiidxdhgtu42tuyb7xeq62ztvu@tvclo336xtpi> Content-Language: en-US From: Imran Shaik In-Reply-To: <5nghgd3lt6vyewd3a7l4kahlxiidxdhgtu42tuyb7xeq62ztvu@tvclo336xtpi> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: aluZDL9sCAM35Ri0F6PSo5M35xNwIjpi X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI5MDA5MiBTYWx0ZWRfX73+wYv1Sjk4B qQmYN0iM52gjc3pqJFNP1zRdN4cs82SJVKT77Yakx+hd4rjRWx7Zi/yoHSi+Kz9uJqpDS0MbGPw AhBeBt4pEC1YS1k/Z4IpAtK7My83P0PMBJL6DdtVJ2X9witAyQ82jDKh8wfW7KGrMeqHJJ/wLZX IqrNrMkMfBmgUA8qTLLzPfMtKbTneLolLKl6f+aIgm+JLZftCv+C3+jIt7YQxgTu0ECKMXM3JG9 PWauFr/ePKuHPKRpJBMSyVH7QBvMFdGa+6nTwZQWYoJ1zLDJ7jco4wqEW4HGKW1RrWGjBdu0Iz6 SXpHaNn9L49mChHoeKzZnPbdFJjAFnpGQZedO/cx7dHmMHBxTMntVXw+sE8hQcsJ2Uz8v/aksFo xUcXB3bDD8Y7aKxdE1TgiWPC+sCbZJaY/XgRvntDHdNmmFOz+NhNYQo85vrE5OIpfL/bnp/Iuwg OF4oLjBZ9mJUK6Uah5A== X-Authority-Analysis: v=2.4 cv=DIG/JSNb c=1 sm=1 tr=0 ts=6a195b18 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=MYhr4v4WboA43l5+MyccHQ==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=Wv3FfvtsC9jmBwEqIE8A:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-GUID: aluZDL9sCAM35Ri0F6PSo5M35xNwIjpi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-29_02,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 spamscore=0 impostorscore=0 adultscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605290092 On 28-05-2026 07:14 pm, Dmitry Baryshkov wrote: > On Thu, May 28, 2026 at 03:37:03PM +0530, Imran Shaik wrote: >> The Qualcomm Shikra Display clock controller reuses the QCM2290 DISPCC, >> but has minor differences with the number of input clocks. Update the >> existing QCM2290 DISPCC bindings using conditional schema so that the >> QCM2290 requirements remain unchanged while accommodating the additional >> clocks required for Shikra. > > According to the IPcat, display clock controller also has (unused) > inputs for the DSI1. Please extend the ABI for Agatti, then extend add > Shikra. > Sure, will add the DSI1 to Agatti as well. Since we are extending the ABI for Agatti, I will remove the clock-names from the bindings and update the DISPCC driver to use the indices-based approach instead. With these updates, the bindings, driver, and Agatti DT must be picked together to avoid any functional issues or ABI breakage. I will explicitly document these details in the commit message in the next series. Thanks, Imran