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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ad52d06cdefsm22310566b.52.2025.05.15.10.56.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 May 2025 10:56:45 -0700 (PDT) Message-ID: <6d7b30b1-60ac-45bf-9ff8-72461f1b21c3@oss.qualcomm.com> Date: Thu, 15 May 2025 19:56:43 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFT v2 13/15] soc: qcom: ubwc: Fix SM6125's ubwc_swizzle value To: Dmitry Baryshkov , Konrad Dybcio Cc: Konrad Dybcio , Bjorn Andersson , Rob Clark , Abhinav Kumar , Akhil P Oommen , Sean Paul , David Airlie , Simona Vetter , Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org References: <20250514-topic-ubwc_central-v2-0-09ecbc0a05ce@oss.qualcomm.com> <20250514-topic-ubwc_central-v2-13-09ecbc0a05ce@oss.qualcomm.com> <9a05d545-1bf2-4f66-8838-b6969ba37baa@oss.qualcomm.com> <466148c9-2461-4140-9ba9-5a3427ec6461@oss.qualcomm.com> <4ec678b4-9e69-4ba0-a59d-f2e0948a73ce@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: OSWRKUwweh54TWZM9z9MP0T_40Q3QziX X-Authority-Analysis: v=2.4 cv=D8dHKuRj c=1 sm=1 tr=0 ts=68262adf cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=S0qm8UsrUeb_ptZHZhEA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE3NiBTYWx0ZWRfX3TeTfK8u7xd6 WLEVSSgV+AJKqc3gWQrgVaOdY9/LwMNxtszuqdm2/dySKmWPGtwqIhe9jmQxKAIPWVBRp0AUlSr 5fNochQFml8WmEPXbS4jn0Io20UDqc8BVnqTmJFp88VLYg8lfkP6S6ssElitC15cm8j815xPvgs QvRoTOL5aTLZBnmafkF1ClHOCvL7gleGAl2IA4i3056tZpjxvv5GIZmEFF12W7nVH7j/gMmvmc0 SiPKnnWt6dsAJrXr7JsVCdMROLDddwmPNGkHqvMrveZwoktKjC1LuBIP5VitsRTgUxo5PVsm4fF l1vBA189VbUDiotFPFBMBHBr2vDjMuq9sYlMj3vxG6oCuKp7puuU5he59+f+pmmdjxA4Ke+Rfae x95PCxtD5FxdIgC1O60Yu93uqcOt1hqZ1c2MkaCAfOyhmt4vu6gUu/35afUZy7jF+/Ppp4Na X-Proofpoint-GUID: OSWRKUwweh54TWZM9z9MP0T_40Q3QziX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_07,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 impostorscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 mlxscore=0 adultscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150176 On 5/15/25 7:15 PM, Dmitry Baryshkov wrote: > On Thu, 15 May 2025 at 19:36, Konrad Dybcio > wrote: >> >> On 5/15/25 6:21 PM, Dmitry Baryshkov wrote: >>> On 15/05/2025 19:18, Konrad Dybcio wrote: >>>> On 5/14/25 10:33 PM, Dmitry Baryshkov wrote: >>>>> On 14/05/2025 23:05, Konrad Dybcio wrote: >>>>>> On 5/14/25 9:23 PM, Dmitry Baryshkov wrote: >>>>>>> On Wed, May 14, 2025 at 05:10:33PM +0200, Konrad Dybcio wrote: >>>>>>>> From: Konrad Dybcio >>>>>>>> >>>>>>>> The value of 7 (a.k.a. GENMASK(2, 0), a.k.a. disabling levels 1-3 of >>>>>>>> swizzling) is what we want on this platform (and others with a UBWC >>>>>>>> 1.0 encoder). >>>>>>>> >>>>>>>> Fix it to make mesa happy (the hardware doesn't care about the 2 higher >>>>>>>> bits, as they weren't consumed on this platform). >>>>>>>> >>>>>>>> Signed-off-by: Konrad Dybcio >>>>>>>> --- >>>>>>>> drivers/soc/qcom/ubwc_config.c | 2 +- >>>>>>>> 1 file changed, 1 insertion(+), 1 deletion(-) >>>>>>>> >>>>>>>> diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c >>>>>>>> index 9caecd071035ccb03f14464e9b7129ba34a7f862..96b94cf01218cce2dacdba22c7573ba6148fcdd1 100644 >>>>>>>> --- a/drivers/soc/qcom/ubwc_config.c >>>>>>>> +++ b/drivers/soc/qcom/ubwc_config.c >>>>>>>> @@ -103,7 +103,7 @@ static const struct qcom_ubwc_cfg_data sm6115_data = { >>>>>>>> static const struct qcom_ubwc_cfg_data sm6125_data = { >>>>>>>> .ubwc_enc_version = UBWC_1_0, >>>>>>>> .ubwc_dec_version = UBWC_3_0, >>>>>>>> - .ubwc_swizzle = 1, >>>>>>>> + .ubwc_swizzle = 7, >>>>>>>> .highest_bank_bit = 14, >>>>>>>> }; >>>>>>> >>>>>>> Add a comment and squash into the patch 1. >>>>>> >>>>>> I don't think that's a good idea, plus this series should be merged >>>>>> together anyway >>>>> >>>>> Well... Granted Rob's comment, I really think the patches should be reordered a bit: >>>>> >>>>> - MDSS: offset HBB by 13 (patch 2) >>>>> - switch drm/msm/mdss and display to common DB (patches 1+3 squashed) >>>>> - get a handle (patch 4) >>>>> - resolve / simplify (patches 5-10, not squashed) >>>>> - fix sm6125 (patch 13) >>>>> - WARN_ON (swizzle != swizzle) or (HBB != HBB) >>>>> - switch to common R/O config, keeping WARN_ON for the calculated values (with the hope to drop them after testing) >>>> >>>> Does this bring any functional benefit? This series is unfun to remix >>> >>> I know the pain. >>> >>> The functional benefit is to have the WARN_ON and side-by-side comparison of common_ubwc_config vs computed ubwc_config for HBB and swizzle. >> >> HBB I agree, since we'll be outsourcing it to yet another driver, swizzle >> should be good enough (tm) - I scanned through the values in the driver >> and couldn't find anything wrong just by eye > > Well. What is the ubwc_swizzle value used for SDM845? I think it > should be 6 according to a6xx_gpu.c and 0 according to msm_mdss.c. > Yes, higher bits are most likely ignored. Still, we'd better have one > correct value. Ehh, so laziness bites after all.. Unfortunately it seems like I don't have a good answer for you - although I can infer a technically valid config for these at the very least: msm8937 msm8998 sc8180x sdm670 sdm845 sm6150 sm7150 sm8150 with the ubwc1.0 platforms receiving all 3 levels and ubwc 2.0/ 3.0 enabling 2/3 this however I'm not sure matches what downstream does.. Konrad