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Fri, 20 Dec 2024 05:51:30 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BK5pTQ6008364 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 20 Dec 2024 05:51:29 GMT Received: from [10.64.68.153] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 19 Dec 2024 21:51:26 -0800 Message-ID: <6d91567b-0cbc-4d85-be38-2467e873e91c@quicinc.com> Date: Fri, 20 Dec 2024 13:51:23 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: sa8775p: fix the secure device bootup issue To: Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Tingwei Zhang , Jinlong Mao References: <20241219025216.3463527-1-quic_jiegan@quicinc.com> <2b4adb2d-29f5-459b-bd85-d5d12876f7eb@oss.qualcomm.com> Content-Language: en-US From: Jie Gan In-Reply-To: <2b4adb2d-29f5-459b-bd85-d5d12876f7eb@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 0E8jCB2TuRa5ANwl6YuxCmAK2oYAB8iQ X-Proofpoint-ORIG-GUID: 0E8jCB2TuRa5ANwl6YuxCmAK2oYAB8iQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 mlxscore=0 clxscore=1015 phishscore=0 impostorscore=0 adultscore=0 spamscore=0 suspectscore=0 mlxlogscore=754 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412200048 On 12/20/2024 5:25 AM, Konrad Dybcio wrote: > On 19.12.2024 3:52 AM, Jie Gan wrote: >> The secure device(fused) cannot bootup with TPDM_DCC device. So >> disable it in DT. >> >> Fixes: 6596118ccdcd ("arm64: dts: qcom: Add coresight nodes for SA8775p") >> Signed-off-by: Jie Gan >> --- > > I was thinking, is there a QFPROM fuse we could read on both > secure and non-secure devices to determine whether all coresight > components will be accessible, and enable them based on that > information? > There are two known TPDM devices had been disabled on secure device. One of these devices is TPDM_DCC. In downstream code, we have an API to check the secure status of the device in TPDM's probe function, to avoid unintentional enable. The downstream API will check the register that controls crash dump functionality in TZ and the crash dump functionality is disabled by default on secure devices. We need to verify if the downstream API is supported by the upstream kernel. We plan to upstream a patch to implement this functionality in the TPDM driver or any other device's driver that needed the functionality. For the time being, we need to disable this TPDM device in DT because the TPDM_DCC will break the bootup process on secure devices. > Konrad Thanks, Jie