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Thu, 12 Oct 2023 16:57:47 GMT Received: from [10.216.13.237] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Thu, 12 Oct 2023 09:57:42 -0700 Message-ID: <6da8dc86-0b9a-488f-9046-9d9d269beeaf@quicinc.com> Date: Thu, 12 Oct 2023 22:27:39 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/3] arm64: dts: qcom: Add interconnect nodes for SDX75 Content-Language: en-US To: Konrad Dybcio , , , , , , CC: , , References: <1696406908-9688-1-git-send-email-quic_rohiagar@quicinc.com> <1696406908-9688-2-git-send-email-quic_rohiagar@quicinc.com> <3a042a26-81b4-4ab3-ba03-a38ae876634b@linaro.org> From: Rohit Agarwal In-Reply-To: <3a042a26-81b4-4ab3-ba03-a38ae876634b@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: KRTXYAmRRvK2hXu9K0uZxZTC_73vYGrm X-Proofpoint-GUID: KRTXYAmRRvK2hXu9K0uZxZTC_73vYGrm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-12_05,2023-10-12_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 adultscore=0 phishscore=0 clxscore=1011 suspectscore=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310120141 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/12/2023 10:18 PM, Konrad Dybcio wrote: > > > On 10/4/23 10:08, Rohit Agarwal wrote: >> Add interconnect nodes to support interconnects on SDX75. >> Also parallely add the interconnect property for UART required >> so that the bootup to shell does not break with interconnects >> in place. >> >> Signed-off-by: Rohit Agarwal >> --- >>   arch/arm64/boot/dts/qcom/sdx75.dtsi | 52 >> +++++++++++++++++++++++++++++++++++++ >>   1 file changed, 52 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi >> b/arch/arm64/boot/dts/qcom/sdx75.dtsi >> index e180aa4..b4723fa 100644 >> --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi >> @@ -8,6 +8,8 @@ >>     #include >>   #include >> +#include >> +#include >>   #include >>   #include >>   #include >> @@ -203,6 +205,19 @@ >>           }; >>       }; >>   +    clk_virt: interconnect-0 { >> +        compatible = "qcom,sdx75-clk-virt"; >> +        #interconnect-cells = <2>; >> +        qcom,bcm-voters = <&apps_bcm_voter>; >> +        clocks = <&rpmhcc RPMH_QPIC_CLK>; >> +    }; >> + >> +    mc_virt: interconnect-1 { >> +        compatible = "qcom,sdx75-mc-virt"; >> +        #interconnect-cells = <2>; >> +        qcom,bcm-voters = <&apps_bcm_voter>; >> +    }; >> + >>       memory@80000000 { >>           device_type = "memory"; >>           reg = <0x0 0x80000000 0x0 0x0>; >> @@ -434,6 +449,9 @@ >>               clock-names = "m-ahb", >>                         "s-ahb"; >>               iommus = <&apps_smmu 0xe3 0x0>; >> +            interconnects = <&clk_virt MASTER_QUP_CORE_0 >> QCOM_ICC_TAG_ALWAYS >> +                     &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; >> +            interconnect-names = "qup-core"; > No qup-config? > > My brain compiler says this would cause a dt checker warning, at least > on next-20231012. If I check the tip, then there is only one interconnect entry. https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/soc/qcom/qcom%2Cgeni-se.yaml#L50 For the debug uart, the qup-config is added. I did check the dtbs_check before sending these patches. Please let me know if I am missing anything. Thanks, Rohit. > > Konrad