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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ1PEPF000037AE.mail.protection.outlook.com (10.167.244.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.8 via Frontend Transport; Wed, 23 Sep 2026 21:40:07 +0000 Received: from [10.236.178.170] (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Wed, 23 Sep 2026 16:40:06 -0500 Message-ID: <6dc03976-faa8-49cb-9b74-680e957f2f9e@amd.com> Date: Wed, 23 Sep 2026 16:40:05 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: "Cheatham, Benjamin" Subject: Re: [PATCH v13 06/15] cxl: Make HDM reset helpers available to built-in PCI code To: Srirangan Madhavan , Alison Schofield , Bjorn Helgaas , Dave Jiang , Davidlohr Bueso , Ira Weiny , Jonathan Cameron , Vishal Verma , , , CC: Alex Williamson , , , Sai Yashwanth Reddy Kancherla , Vishal Aslot , Manish Honap , Jiandi An , Richard Cheng , References: <20260922083924.2451158-1-smadhavan@nvidia.com> <20260922083924.2451158-7-smadhavan@nvidia.com> Content-Language: en-US In-Reply-To: <20260922083924.2451158-7-smadhavan@nvidia.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: IEjoeZUZmvB3XBxLeEMJIP0wPxwHHy0XWpTKQP6H4mKmWpll3gcPujWXagkRl4xBpxNmo1aawKHGurtBr7wrYBAiazSng+YJ5pROsC+vtos5rDMuc/pvgelEBDGj5PNuZqqAJ8tT3fHvKw0FDttzJ30k291F9oy4m7xXvclgaiOPMGKtxbs8yhJcobDOm+e09v+FkeWv8cZ1gaJzB61lt1UMeDkFjSSTU6X+ubs8gDe7BYZQ37FhBGPtbdxuCdL5FM5YVfNxqmVpZv2t4I0d5Vtw+BMNiHEzrREwz9+L3PaAnY/eAPuJEAhF3jioDWmIEjnu2nGLsbA3ScE2cGhNctK9Umg+FtBtHNGgtZ5E6TgSgy3cT/bmFMRs51exVM9jjEET8lii4Y1blnC5EF1y62WNNGYzw8e9Wp9t0Jxgn9JYKM3J2pgcYopXQT8bdLHC X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2026 21:40:07.9653 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c1b61132-d53d-4ce3-ff21-08df19bb3cd9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000037AE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB5626 On 9/22/2026 3:39 AM, Srirangan Madhavan wrote: > PCI can be built in while CXL_BUS is modular, so PCI reset code cannot > depend on helpers provided by the cxl_core module. > > Build the HDM resource helpers under CONFIG_CXL_RESET and restrict their > exports to cxl_core. > I think you should squash this patch into 3/15. Having this earlier does two things: 1) it makes it more clear why you're moving everything earlier in the set, and 2) bisects across the pass 3 patches will all result in the same configuration. An alternative option would be to refactor the preceding 3 patches in-place and then move all of the helpers to this file in this patch, either would work. > Signed-off-by: Srirangan Madhavan > --- > drivers/cxl/Kconfig | 4 ++++ > drivers/cxl/core/Makefile | 2 +- > drivers/cxl/core/resource.c | 4 ++++ > tools/testing/cxl/Kbuild | 1 - > 4 files changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig > index 80aeb0d556bd..0cd704670735 100644 > --- a/drivers/cxl/Kconfig > +++ b/drivers/cxl/Kconfig > @@ -6,6 +6,7 @@ menuconfig CXL_BUS > select FW_UPLOAD > select PCI_DOE > select FIRMWARE_TABLE > + select CXL_RESET > select NUMA_KEEP_MEMINFO if NUMA_MEMBLKS > select FWCTL if CXL_FEATURES > help > @@ -244,3 +245,6 @@ config CXL_ATL > depends on ACPI_PRMT && AMD_NB > > endif > + > +config CXL_RESET > + bool > diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile > index 57995777af0d..30470799e059 100644 > --- a/drivers/cxl/core/Makefile > +++ b/drivers/cxl/core/Makefile > @@ -1,12 +1,12 @@ > # SPDX-License-Identifier: GPL-2.0 > obj-$(CONFIG_CXL_BUS) += cxl_core.o > +obj-$(CONFIG_CXL_RESET) += resource.o This file should probably be called reset.c instead of resource.c to match the Kconfig functionality. > obj-$(CONFIG_CXL_SUSPEND) += suspend.o > > ccflags-y += -I$(srctree)/drivers/cxl > CFLAGS_trace.o = -DTRACE_INCLUDE_PATH=. -I$(src) > > cxl_core-y := port.o > -cxl_core-y += resource.o > cxl_core-y += pmem.o > cxl_core-y += regs.o > cxl_core-y += memdev.o > diff --git a/drivers/cxl/core/resource.c b/drivers/cxl/core/resource.c > index ea0d855e5549..1b4742622054 100644 > --- a/drivers/cxl/core/resource.c > +++ b/drivers/cxl/core/resource.c > @@ -3,6 +3,7 @@ > #include > #include > #include > +#include > #include > > #include "cxl.h" > @@ -12,6 +13,7 @@ struct cxl_rwsem cxl_rwsem = { > .region = __RWSEM_INITIALIZER(cxl_rwsem.region), > .dpa = __RWSEM_INITIALIZER(cxl_rwsem.dpa), > }; > +EXPORT_SYMBOL_FOR_MODULES(cxl_rwsem, "cxl_core"); > > static void cxld_set_interleave(struct cxl_decoder_config *config, u32 *ctrl) > { > @@ -100,8 +102,10 @@ void cxl_commit_start(void __iomem *hdm, struct cxl_decoder_settings *settings) > lockdep_assert_held(&cxl_rwsem.dpa); > setup_hw_decoder(hdm, settings); > } > +EXPORT_SYMBOL_FOR_MODULES(cxl_commit_start, "cxl_core"); > > int cxl_commit_wait(void __iomem *hdm, struct cxl_decoder_settings *settings) > { > return cxld_await_commit(hdm, settings->config.id); > } > +EXPORT_SYMBOL_FOR_MODULES(cxl_commit_wait, "cxl_core"); > diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild > index 6c09932587ce..2be1df80fcc9 100644 > --- a/tools/testing/cxl/Kbuild > +++ b/tools/testing/cxl/Kbuild > @@ -60,7 +60,6 @@ cxl_core-y += $(CXL_CORE_SRC)/memdev.o > cxl_core-y += $(CXL_CORE_SRC)/mbox.o > cxl_core-y += $(CXL_CORE_SRC)/pci.o > cxl_core-y += $(CXL_CORE_SRC)/hdm.o > -cxl_core-y += $(CXL_CORE_SRC)/resource.o If you squash this patch you also don't need to bother adding/removing this. > cxl_core-y += $(CXL_CORE_SRC)/pmu.o > cxl_core-y += $(CXL_CORE_SRC)/cdat.o > cxl_core-$(CONFIG_TRACING) += $(CXL_CORE_SRC)/trace.o