From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752093AbdAaSHT (ORCPT ); Tue, 31 Jan 2017 13:07:19 -0500 Received: from smtprelay.synopsys.com ([198.182.47.9]:49208 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751309AbdAaSDQ (ORCPT ); Tue, 31 Jan 2017 13:03:16 -0500 Subject: Re: [PATCH v2 4/4] ARCv2: IRQ: Set a default priority for all core interrupts To: Yuriy Kolerov , References: <1485863124-26426-1-git-send-email-yuriy.kolerov@synopsys.com> <1485863124-26426-5-git-send-email-yuriy.kolerov@synopsys.com> CC: , , Newsgroups: gmane.linux.kernel.arc,gmane.linux.kernel From: Vineet Gupta Message-ID: <6dd5743d-cf5b-a65e-86fe-86fff2777e81@synopsys.com> Date: Tue, 31 Jan 2017 09:54:09 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.7.0 MIME-Version: 1.0 In-Reply-To: <1485863124-26426-5-git-send-email-yuriy.kolerov@synopsys.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.10.161.49] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/31/2017 03:45 AM, Yuriy Kolerov wrote: > After reset all interrupts in the core interrupt controller has > the highest priority P0. If the platform supports Fast IRQs and > has more than 1 banks of registers then CPU automatically switch > banks of registers when P0 interrupt comes. > > The problem is that the kernel expects that by default switching > of banks is not used by all interrupts. It is necessary to set a > default nonzero priority for all available interrupts to avoid > undefined behaviour. > > Signed-off-by: Yuriy Kolerov > --- > arch/arc/kernel/intc-arcv2.c | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c > index 31246cc..d4fa4a5 100644 > --- a/arch/arc/kernel/intc-arcv2.c > +++ b/arch/arc/kernel/intc-arcv2.c > @@ -22,7 +22,7 @@ > */ > void arc_init_IRQ(void) > { > - unsigned int tmp, irq_prio; > + unsigned int tmp, irq_prio, i; > > struct bcr_irq_arcv2 irq_bcr; > > @@ -62,6 +62,16 @@ void arc_init_IRQ(void) > irq_prio + 1, ARCV2_IRQ_DEF_PRIO, > irq_bcr.firq ? " FIRQ (not used)":""); > > + /* > + * Set a default priority for all available interrupts to prevent > + * switching of register banks if Fast IRQ and multiple register banks > + * are supported by CPU. > + */ > + for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) { > + write_aux_reg(AUX_IRQ_SELECT, i); > + write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); > + } > + This itself is fine. However going forward can we move to the genirq irq_cpu_online() etc instead of doing this in our platform per cpu hook ? https://www.linux-mips.org/archives/linux-mips/2011-03/msg00115.html > /* setup status32, don't enable intr yet as kernel doesn't want */ > tmp = read_aux_reg(ARC_REG_STATUS32); > tmp |= STATUS_AD_MASK | (ARCV2_IRQ_DEF_PRIO << 1); >