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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c9562ea8sm161470666b.93.2025.01.10.04.06.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Jan 2025 04:06:24 -0800 (PST) Message-ID: <6e1ed6f3-100d-4e45-a9ee-251513749f57@oss.qualcomm.com> Date: Fri, 10 Jan 2025 13:06:22 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: add missing cache node for cpu1 To: neil.armstrong@linaro.org, Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250109-topic-sm8650-cpu1-missing-cache-v1-1-0e85148a48a8@linaro.org> <549d15ae-34db-497c-89d7-c9b9c18d8681@oss.qualcomm.com> <99747e37-1288-4d70-a678-0a73bb4c3b3f@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: E0AevaVduHAJgm9A-znkicVRLgvZzoU1 X-Proofpoint-ORIG-GUID: E0AevaVduHAJgm9A-znkicVRLgvZzoU1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 spamscore=0 mlxscore=0 priorityscore=1501 phishscore=0 mlxlogscore=999 suspectscore=0 malwarescore=0 bulkscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501100094 On 10.01.2025 10:49 AM, Neil Armstrong wrote: > On 10/01/2025 10:44, Neil Armstrong wrote: >> On 09/01/2025 19:30, Konrad Dybcio wrote: >>> On 9.01.2025 4:24 PM, Neil Armstrong wrote: >>>> Add the missing l2-cache node for the cpu1 >>>> >>>> Fixes: 20eb2057b3e4 ("arm64: dts: qcom: sm8650: change labels to lower-case") >>>> Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi") >>>> Signed-off-by: Neil Armstrong >>>> --- >>> >>> subject: missing `sm8650:` >> >> Damn >> >>> >>>>   arch/arm64/boot/dts/qcom/sm8650.dtsi | 7 +++++++ >>>>   1 file changed, 7 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi >>>> index 86684cb9a9325618ddb74458621cf4bbdc1cc0d1..832f3a2c400e8348847bc24b27397e2a0dc08db8 100644 >>>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi >>>> @@ -119,6 +119,13 @@ cpu1: cpu@100 { >>>>               qcom,freq-domain = <&cpufreq_hw 0>; >>>>               #cooling-cells = <2>; >>>> + >>>> +            l2_100: l2-cache { >>>> +                compatible = "cache"; >>>> +                cache-level = <2>; >>>> +                cache-unified; >>>> +                next-level-cache = <&l3_0>; >>>> +            }; >>>>           }; >>> >>> You likely wanted to hook up this new node to CPU1 as well. >>> >>> Reading some Arm docs [1], it seems like with A520 specifically, both shared >>> and unique cache slices are permitted, depending on whether they're >>> implemented as single- or dual-core complexes (not to be confused with >>> multi-threading) >>> >>> [2] suggests CA720s always have their own cache pools >>> >>> In 8650's case, the slowest cluster has a shared L2 cache, whereas cores 2-7 >>> have their own pools, so this patch is incorrect. >> >> Damn you're right, so the cpu1 cache should be linked to the cpu0 cache somehow > > Well, stupid me, it's already done... sorry for the noise and thx for your review cpu3 should still get its own one Konrad