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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BL02EPF00021F6D.mail.protection.outlook.com (10.167.249.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.245.5 via Frontend Transport; Thu, 16 Jul 2026 18:25:24 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Thu, 16 Jul 2026 13:25:21 -0500 Received: from [172.31.184.125] (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Thu, 16 Jul 2026 13:25:17 -0500 Message-ID: <6e385952-9885-4736-8501-45aafe4310cd@amd.com> Date: Thu, 16 Jul 2026 23:55:16 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] sched: set TIF_NEED_RESCHED before calling __trace_set_need_resched() To: Will Deacon , Peter Zijlstra CC: Gabriele Monaco , Sechang Lim , Ingo Molnar , Juri Lelli , Vincent Guittot , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , , Mark Rutland References: <6cbcc3ea742b92b6a34b5994f5498c7611beac7e.camel@redhat.com> <5f47566b-88f4-458d-87a4-7794e6ba8203@amd.com> <20260630203408.GG48970@noisy.programming.kicks-ass.net> <20260701065447.GI48970@noisy.programming.kicks-ass.net> <14abaec8-05ca-4034-b153-b993ed60a1fb@amd.com> <20260701084939.GE751831@noisy.programming.kicks-ass.net> Content-Language: en-US From: K Prateek Nayak In-Reply-To: Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1702kjfF73UV6ycovECqS0uNVHsP5FVgbmZsaRpqddidWXGFxjDw1gs/bNtebXQXyiAOBZIKzkZUj367kKFMOXyo6kcRihRRx391y2mICWSVH6TM0096IU9OJsbZ3zp+sseojOWcbNbKqLnCoKEc+sf3WF5gWveqfij5fTp8XClXl8n7mV86o89bPgxuUITgPSzYXC3MTrdWtJCE8q5EO9AaeG3xTYPqn4NglJk7SILfT8BqcfEvPO44HWVqVBCkDbYze7UYamw8c1fuzSgczsHHY2C3i4jgcuW+OE1P1M5Vk0hcjog4AfV24m7V0kMWnZZ7Y0bmBH6AQqNLES44PXtOU2VU8SSMD2T8kLiVF+7v1Zlp1tYmfXrvF3NAeqWwnPGqLAcQQinc4fR9c7NtuPDm4+LSE4B0UIxHdS2EKn0VvXu2h8++J4Lzuccr8STL X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jul 2026 18:25:24.4623 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 22a65200-79ab-4863-7639-08dee3679a6c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7494 Hello Will, On 7/16/2026 8:39 PM, Will Deacon wrote: > On Wed, Jul 01, 2026 at 10:49:39AM +0200, Peter Zijlstra wrote: >> On Wed, Jul 01, 2026 at 01:39:23PM +0530, K Prateek Nayak wrote: >>> Hello Peter, >>> >>> On 7/1/2026 12:24 PM, Peter Zijlstra wrote: >>>>> @@ -1204,16 +1217,16 @@ static void __resched_curr(struct rq *rq, int tif) >>>>> cpu = cpu_of(rq); >>>>> >>>>> if (cpu == smp_processor_id()) { >>>>> - set_ti_thread_flag(cti, tif); >>>>> + int set = test_and_set_ti_thread_flag(cti, tif); >>>>> + >>>>> + if (trace_sched_set_need_resched_tp_enabled() && !set) >>>>> + trace_call__sched_set_need_resched_tp(curr, cpu, tif); >>>>> if (tif == TIF_NEED_RESCHED) >>>>> set_preempt_need_resched(); >>>>> - trace_sched_set_need_resched_tp(curr, cpu, tif); >>>>> return; >>>>> } >>>> >>>> I can't help but notice that the local and !POLLING cases show >>>> remarkable similarity. Just not sure extracting that isn't going to make >>>> a mess. >>>> >>>> Anyway, yes this looks about right. >>> >>> If the fetch_or() based path is okay for !POLLING and local cases which >>> uses a slightly (vastly?) worse instruction to set the ti->flags, we can >>> instead do: >>> >> Tempting, but at least arm64 would have to agree I think. That said, I >> wonder why ARM64 doesn't use LDXR+WFE for idle, just like we have >> MONITOR+MWAIT. >> >> Probably too damn many idle flavours to deal with or somesuch. > > I think the problem is a combination of: > > 1. You probably want to enter a deeper sleep state after polling for a > bit, but you might just get stuck in the WFE if you don't get an > update. But you can idle with scheduler tick enabled with WFE and that should allow you to retrospect and go deeper at the next tick if needed, no? > 2. An IRQ doesn't wake WFE if IRQs are disabled (this is different to > WFI). I'm out of my depths here but the on x86 side mwait_idle() does an MWAIT with interrupts enabled. The polling flag being set is simply an optimization for the IPI sender to set RESCHED bit instead of sending a physical IPI - an external interrupt is still possible and will break out of idle. Also, the other question on the thread was: Is try_cmpxchg() much worse than a test_and_set_ti_thread_flag() (which uses test_and_set_bit()) on ARM64? The full diff in https://lore.kernel.org/lkml/14abaec8-05ca-4034-b153-b993ed60a1fb@amd.com/ replaces a test_and_set_ti_thread_flag() path with a try_cmpxchg() one and we were wondering if the code unification is worth the performance lost. -- Thanks and Regards, Prateek