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Thu, 10 Jul 2025 16:12:22 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id EA7F440044; Thu, 10 Jul 2025 16:11:23 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 002DFAF9A59; Thu, 10 Jul 2025 16:10:46 +0200 (CEST) Received: from [10.48.86.182] (10.48.86.182) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 10 Jul 2025 16:10:46 +0200 Message-ID: <6e44163a-eae3-49bb-8c05-32437d517451@foss.st.com> Date: Thu, 10 Jul 2025 16:10:44 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] arm64: dts: st: fix timer used for ticks To: Marc Zyngier CC: Alexandre TORGUE , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , , , , References: <20250515151238.1.I85271ddb811a7cf73532fec90de7281cb24ce260@changeid> <86ikm2f0y2.wl-maz@kernel.org> Content-Language: en-US From: Patrick DELAUNAY In-Reply-To: <86ikm2f0y2.wl-maz@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-10_03,2025-07-09_01,2025-03-28_01 Hi Mark, On 5/15/25 15:39, Marc Zyngier wrote: > On Thu, 15 May 2025 14:12:39 +0100, > Patrick Delaunay wrote: >> Remove always-on on generic ARM timer as the clock source provided by >> STGEN is deactivated in low power mode, STOP1 by example. >> >> Fixes: 5d30d03aaf78 ("arm64: dts: st: introduce stm32mp25 SoCs family") >> Signed-off-by: Patrick Delaunay >> --- >> >> arch/arm64/boot/dts/st/stm32mp251.dtsi | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi >> index 8d87865850a7..74c5f85b800f 100644 >> --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi >> +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi >> @@ -150,7 +150,7 @@ timer { >> , >> , >> ; >> - always-on; >> + arm,no-tick-in-suspend; > That's amusing, because these two properties literally describe > opposite behaviours (from an optimisation to a HW bug). > > I'm also pretty sure 99% of the DTs in the tree that have the > always-on property are wrong. yes it was a bug in the initial device tree, detected when we implement the low power support in STMicroelectronics downtream. STGEN, the root source of ARM generic timer in STM32MP25 is stopped in low power states. > >> }; >> >> soc@0 { > I don't want to sound rude or anything, but the guy you Cc'd on an > @arm.com will not reply (and hasn't been replying for almost 6 years). your not rude and It is my error, sorry I search email for "Marc Zyngier " in Linux source tree.... and I use a bad address. For information, I upstream this patch after the remark on patch by Christian Bruel: [PATCH 3/3] arm64: dts: st: add st,stm32mp2-cortex-a7-gic in intc node in stm32mp251.dtsi https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250403122805.1574086-4-christian.bruel@foss.st.com/ >   While reviewing a DT patch of mine related to the interrupt-controller, I had the following  >  comment from Marc Zyngier (GIC Maintainer) " Then while you're at it, you may want to  >  consider removing the "always-on" property in the timer, because I'm pretty sure the   > comparator goes down in low power mode on A53 and A35, and loses its value. >   In general, only VMs can make use of this property. " > > Thanks, > > M. > Thanks