From: Andrew Lunn <andrew@lunn.ch>
To: Diogo Silva <diogompaissilva@gmail.com>
Cc: hkallweit1@gmail.com, linux@armlinux.org.uk, davem@davemloft.net,
edumazet@google.com, kuba@kernel.org, pabeni@redhat.com,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
marex@denx.de, tolvupostur@gmail.com
Subject: Re: [PATCH] net: phy: ti: add PHY_RST_AFTER_CLK_EN flag
Date: Sun, 3 Nov 2024 16:20:33 +0100 [thread overview]
Message-ID: <6e5298c0-eded-4fd2-8ce6-52d4239da53c@lunn.ch> (raw)
In-Reply-To: <20241102151504.811306-1-paissilva@ld-100007.ds1.internal>
On Sat, Nov 02, 2024 at 04:15:05PM +0100, Diogo Silva wrote:
> From: Diogo Silva <diogompaissilva@gmail.com>
>
> DP83848 datasheet (section 4.7.2) indicates that the reset pin should be
> toggled after the clocks are running. Add the PHY_RST_AFTER_CLK_EN to
> make sure that this indication is respected.
>
> In my experience not having this flag enabled would lead to, on some
> boots, the wrong MII mode being selected if the PHY was initialized on
> the bootloader and was receiving data during Linux boot.
>
> Signed-off-by: Diogo Silva <diogompaissilva@gmail.com>
This should be merged to net.
Fixes: 34e45ad9378c ("net: phy: dp83848: Add TI DP83848 Ethernet PHY")
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
next prev parent reply other threads:[~2024-11-03 15:20 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-02 15:15 Diogo Silva
2024-11-02 17:03 ` Andrew Lunn
2024-11-03 10:24 ` Diogo Silva
2024-11-03 15:20 ` Andrew Lunn [this message]
2024-11-06 1:50 ` patchwork-bot+netdevbpf
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