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Sun, 10 May 2026 14:23:13 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , Subject: [PATCH v5 3/6] iommu/arm-smmu-v3: Suppress EVTQ/PRIQ events in kdump kernel Date: Sun, 10 May 2026 14:23:02 -0700 Message-ID: <6e5828f3288aed6f9e9f4e0ca54e7fbd9f439274.1778416609.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0002256E:EE_|MN0PR12MB5956:EE_ X-MS-Office365-Filtering-Correlation-Id: ecb94f07-4085-4892-1e46-08deaeda5da5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|36860700016|1800799024|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: aaV897NE9K4IWIavoxdOA4drbCDAA/XHcl5OfMhjvtxtbEQSNYDw57l80nK8tjPDVHgg0VIlJwJoXYhlwObY37oU0HmjaEpkJ0D/O234b/+YDwIA+G0QZzmiorF/RUINmzetm+9E4mH7q0NHqbOGJTcl39tsWJ6zBNpCardkbrg2xGZ4wJHTHxwm99wcTQuUZf53FVjYL8Rdz7fYWbakCllAE3kAg/WhHiN/tH3BVfg37uPHB4d/2bPbHedc1c4ftaPQB9SFnrm8BTZnn0/pXZU+GRgr8s1vch/aB9UvvUx0qp6kZ+/TDqaczuB+tE9ZzzElCRMJgfdq7TJcGjD+jTxkQg06aj9f+bKkok3I0UMixX0qnOHc4bnRJuXf9ej1oOwnXE7OwqyR0wJd1LMWRyroJAhx4DrzF1nrS3EIgDaog92a72bQdrDGNYJU9xExNwwa06OLmR7xOFwFFt8NddmQoMXbqJUO8OTlt4zaf4NfTV/hIs92pchYsRfE3/N2DaiO6RToeo1qgfvvJ+QeCkIgsqxQJv6k9XK7lYrUnteKYLaDvteK6LKjq/rXMrei546jq1NHR52aYElR5yViuD47PfSCS9utgYVZhpbtotgDzzkj7fRQIAOCMzbAY3Eq8Ru0v59gUHRlR+yjTPautbQenAw86Ao+1mRuqD/cQpIbRzntfs5GJy92STYj1dn+KfIXSYXIh/COX9kqHK5JQT1tBFBca6KqM/dwpiY5U3o= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(36860700016)(1800799024)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2G+Wk/IAvbRi6BATfPdAqvIGcLliC4Ha5LFKbNkUrKVXXI8uu/pHARrnGTP7pXbQd2AyowZ/0l4D/HOj9O99EX3NMgUCBABUPuD5uvczG+thiOMPA0BlcDxHDQt0oC+dbmIP5vknk8WNPmK3yCJhBfsjE+SDpzSmW9lwBeWRfr1hQFNQ3GqqyLRA6pvYXuQ6lJWcgQXs0MDEIG7m2zXurhkDqe5QDJm1CSP7kHLbOYrGevi2FVEQHqn/ahJ1G8HG6PB72ergVR+FMi2kbp6ALzihqSNlCeujhXwCI8wWFViaYRNygsdpWMy1KDIdPLDhekWDqiRgP76E0MRbO2wioFBrP7Te4vjUDFcmCFcDKdujVtE28TNKh4RiCiv+1NRmPFgVxO+SZCppNVCnGSvJ9YqwqCH8n+Xaqrat2QXMQMC/xz/csI/X50BX9vOMvJ8C X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2026 21:23:22.8478 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ecb94f07-4085-4892-1e46-08deaeda5da5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0002256E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5956 In kdump cases, the crashed kernel's CDs and page tables can be corrupted, which could trigger event spamming. Also, we cannot serve page requests. Skip the IRQ setup for EVTQ/PRIQ in arm_smmu_setup_irqs(), and guard the thread functions against being entered via a combined-IRQ delivery while the queue is disabled. Fixes: b63b3439b856 ("iommu/arm-smmu-v3: Abort all transactions if SMMU is enabled in kdump kernel") Cc: stable@vger.kernel.org # v6.12+ Reviewed-by: Kevin Tian Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 23 +++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 579c8af82d6b6..ebb0826d74541 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2364,6 +2364,14 @@ static irqreturn_t arm_smmu_evtq_thread(int irq, void *dev) static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); + /* + * A combined IRQ might call into this function with the queue disabled. + * E.g. kdump, where stale HW PROD vs SW CONS would drive a bogus drain + * and a CONS write to a disabled queue. + */ + if (!(readl_relaxed(smmu->base + ARM_SMMU_CR0) & CR0_EVTQEN)) + return IRQ_NONE; + do { while (!queue_remove_raw(q, evt)) { arm_smmu_decode_event(smmu, evt, &event); @@ -2432,6 +2440,14 @@ static irqreturn_t arm_smmu_priq_thread(int irq, void *dev) struct arm_smmu_ll_queue *llq = &q->llq; u64 evt[PRIQ_ENT_DWORDS]; + /* + * A combined IRQ might call into this function with the queue disabled. + * E.g. kdump, where stale HW PROD vs SW CONS would drive a bogus drain + * and a CONS write to a disabled queue. + */ + if (!(readl_relaxed(smmu->base + ARM_SMMU_CR0) & CR0_PRIQEN)) + return IRQ_NONE; + do { while (!queue_remove_raw(q, evt)) arm_smmu_handle_ppr(smmu, evt); @@ -5056,7 +5072,10 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu) static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) { int ret, irq; - u32 irqen_flags = IRQ_CTRL_EVTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN; + u32 irqen_flags = IRQ_CTRL_GERROR_IRQEN; + + if (!is_kdump_kernel()) + irqen_flags |= IRQ_CTRL_EVTQ_IRQEN; /* Disable IRQs first */ ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL, @@ -5082,7 +5101,7 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) } else arm_smmu_setup_unique_irqs(smmu); - if (smmu->features & ARM_SMMU_FEAT_PRI) + if (!is_kdump_kernel() && (smmu->features & ARM_SMMU_FEAT_PRI)) irqen_flags |= IRQ_CTRL_PRIQ_IRQEN; /* Enable interrupt generation on the SMMU */ -- 2.43.0