From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751889AbdAYNFP (ORCPT ); Wed, 25 Jan 2017 08:05:15 -0500 Received: from lelnx194.ext.ti.com ([198.47.27.80]:13022 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751478AbdAYNFO (ORCPT ); Wed, 25 Jan 2017 08:05:14 -0500 Subject: Re: [PATCH] clk: ti: divider: Add the table parsing to get the best divider value To: Keerthy References: <1480669543-16197-1-git-send-email-j-keerthy@ti.com> <98780c76-0ba8-85ec-ca01-392f36fa91ad@ti.com> CC: , , , , From: Tero Kristo Message-ID: <6e5a0ca7-c994-8e38-8e35-dd2ac10180ca@ti.com> Date: Wed, 25 Jan 2017 15:05:08 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <98780c76-0ba8-85ec-ca01-392f36fa91ad@ti.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 25/01/17 12:37, Keerthy wrote: > > > On Friday 02 December 2016 02:35 PM, Keerthy wrote: >> Currently the divider selection logic blindly divides the parent_rate >> by the clk rate and gives the divider value for the divider clocks >> which do not have the CLK_SET_RATE_PARENT flag set. Add the clk divider >> table parsing to get the closest divider available in the table >> provided via Device tree. >> >> The code is pretty much taken from: drivers/clk/clk-divider.c. >> and used here to fix up the best divider selection logic. > > A gentle ping on this patch. This applies cleanly on the next branch as > on today. Let me know if this needs to be rebased. > > - Keerthy > >> >> Signed-off-by: Keerthy >> Reported-by: Richard Woodruff Acked-by: Tero Kristo Stephen / Michael, can you pick this up? -Tero >> --- >> drivers/clk/ti/divider.c | 31 ++++++++++++++++++++++++++++++- >> 1 file changed, 30 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c >> index b4e5de1..6bb8778 100644 >> --- a/drivers/clk/ti/divider.c >> +++ b/drivers/clk/ti/divider.c >> @@ -140,6 +140,35 @@ static bool _is_valid_div(struct clk_divider >> *divider, unsigned int div) >> return true; >> } >> >> +static int _div_round_up(const struct clk_div_table *table, >> + unsigned long parent_rate, unsigned long rate) >> +{ >> + const struct clk_div_table *clkt; >> + int up = INT_MAX; >> + int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); >> + >> + for (clkt = table; clkt->div; clkt++) { >> + if (clkt->div == div) >> + return clkt->div; >> + else if (clkt->div < div) >> + continue; >> + >> + if ((clkt->div - div) < (up - div)) >> + up = clkt->div; >> + } >> + >> + return up; >> +} >> + >> +static int _div_round(const struct clk_div_table *table, >> + unsigned long parent_rate, unsigned long rate) >> +{ >> + if (!table) >> + return DIV_ROUND_UP(parent_rate, rate); >> + >> + return _div_round_up(table, parent_rate, rate); >> +} >> + >> static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, >> unsigned long *best_parent_rate) >> { >> @@ -155,7 +184,7 @@ static int ti_clk_divider_bestdiv(struct clk_hw >> *hw, unsigned long rate, >> >> if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { >> parent_rate = *best_parent_rate; >> - bestdiv = DIV_ROUND_UP(parent_rate, rate); >> + bestdiv = _div_round(divider->table, parent_rate, rate); >> bestdiv = bestdiv == 0 ? 1 : bestdiv; >> bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv; >> return bestdiv; >>