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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b79f445967fsm349282966b.10.2025.12.05.03.58.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 05 Dec 2025 03:58:30 -0800 (PST) Message-ID: <6e6ecdbf-f3cb-4d7e-a679-4640d6603ac8@oss.qualcomm.com> Date: Fri, 5 Dec 2025 12:58:27 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 2/3] arm64: dts: qcom: qcs8300: Add CCI definitions To: Nihal Kumar Gupta , Vikram Sharma Cc: bryan.odonoghue@linaro.org, mchehab@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, hverkuil-cisco@xs4all.nl, cros-qcom-dts-watchers@chromium.org, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, quic_svankada@quicinc.com, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ravi Shankar , Vishal Verma References: <3f1dbf91-f967-44dc-bb21-25fdcbbc8db2@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <3f1dbf91-f967-44dc-bb21-25fdcbbc8db2@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: EYIwKuhGQfLAe6qjqYhzR2d4syZOnu7g X-Proofpoint-ORIG-GUID: EYIwKuhGQfLAe6qjqYhzR2d4syZOnu7g X-Authority-Analysis: v=2.4 cv=XeOEDY55 c=1 sm=1 tr=0 ts=6932c8e8 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=COk6AnOGAAAA:8 a=JE8FtNjG4eDj_IBO3V8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA1MDA4NiBTYWx0ZWRfX9fuL03EBnJ2b 2BbHRWZ5caieCAA6Aeg/gZybNg/e/WBPql8qYXwwmmXbesrUiCuJYGmelJjTsCKwIRGliHOxMkX 6L2Cbv6glzy/mBOUoRtwMTAvZnniMr8mWMPDDIXR3UuUYL942VfjRMMqpGtr55U9RoMJsNpoYHT 1+Qu1BltIqxcx19F/fgVxKGv4jCoFCb+pyHlid6E6Oiocq1NtE0ZPgVZLAmZIDYAcm230Wm9OFf E5uELT0wNRa9GLJYaIQFhqh/TLj5//ui8UryHJG/ENpLv326b9Qkp1pl1wOh82nTxOWxvD8jPmi s2278TapjQ6Ido0pnu+JJp/FfwjwsUbuGhp6G+xLFQtkGjy2ruAZnaK+CcuQ+yLHDD19wfzNgUC MAiSjMjQTJwyRDZuAGhJzle0n4g+wQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-05_04,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 adultscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 clxscore=1015 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512050086 On 12/2/25 8:35 AM, Nihal Kumar Gupta wrote: > > > On 11/26/25 9:10 AM, Vikram Sharma wrote: >>> From: Nihal Kumar Gupta >>> >>> Qualcomm QCS8300 SoC contains three Camera Control Interface (CCI). >>> Compared to Lemans, the key difference is in SDA/SCL GPIO assignments >>> and number of CCIs. >> [...] >> >>> @@ -5071,6 +5182,240 @@ tlmm: pinctrl@f100000 { >>> #interrupt-cells = <2>; >>> wakeup-parent = <&pdc>; >>> >>> + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state { >>> + pins = "gpio73"; >>> + function = "gpio"; >>> + drive-strength = <2>; >>> + bias-disable; >>> + }; >> I'm not sure whether I was unclear, but my intention was to ask you to move the MCLK pin definitions to the SoC DTSI, because that comes from the design of the platform and doesn't vary between end products. >> >> GPIO_73 being related to a voltage regulator is strictly a property of the EVK. > > MCLK pin definitions are already present under the tlmm block in SoC dtsi(monaco.dtsi) as required by the pinctrl subsystem(qcom,qcs8300-tlmm.yaml). The latter part of your sentence refers to the pin definition having to end up under TLMM in the final DT, which it will be regardless of where exactly in the source files it appears. What I'm alluding to is that we organize some of these definitions in a specific source file to make logical sense and keep them within relevant scope (i.e. you shouldn't be able to refer to a board X-specific setting from board Y DT - that's unnecessary room for error, whereas pin definitions that are a result of the SoC design make sense to be shared) > Are you suggesting they shouldn’t be part of TLMM in the SoC DTSI? This doesn’t align with the YAML file. That's not exactly true, the YAML file you're referencing only lists the allowed entries in the 'function' property of the pinmux subnodes. The DT checker makes no effort to analyze your file structure, it only makes sure that you're not adding illegal properties (or lacking required ones) for a given device described by a binding. > Regarding GPIO_73: Noted. I will move it to monaco-evk.dts under the tlmm section. > > Below are the example snippets: > In monaco.dtsi (SoC level): > tlmm: pinctrl@... { > cam_mclk0_default: cam-mclk0-default-state { > pins = "gpio67"; > function = "cam_mclk"; > drive-strength = <2>; > }; > .... > }; > > In monaco-evk.dts (Board level): > &tlmm { > cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state { > pins = "gpio73"; > function = "gpio"; > drive-strength = <2>; > bias-disable; > }; That was my entire points, thanks Konrad