Re: [PATCH 5/7] ARM: dts: qcom: msm8226: Add CPU frequency scaling support

[Konrad Dybcio <konrad.dybcio@linaro.org>]

On 19.06.2024 11:02 PM, Luca Weiss wrote:
> Add a node for the a7pll with its frequencies. With this we can use the
> apcs-kpss-global driver for the apcs node and use the apcs to scale the
> CPU frequency according to the opp-table.
> 
> At the same time unfortunately we need to provide the gcc node xo_board
> instead of the XO via rpmcc since otherwise we'll have a circular
> dependency between apcs, gcc and the rpm.

Hm.. thinking of a solution to that, should we maybe split the mux/clk
part of APCS into a subnode and bind the clk device to that?

Dmitry, Bjorn, thoughts?

[...]
> +
> +		opp-600000000 {

Can't find this one in the random msm-3.10 I have

> +			opp-hz = /bits/ 64 <600000000>;
> +		};
> +
> +		opp-787200000 {
> +			opp-hz = /bits/ 64 <787200000>;
> +		};
> +
> +		/* Higher CPU frequencies need speedbin support */

1190400 kHz seems to also be a supported-across-the-board one.. unless the
watch edition shuffled things around with a newer tree


> +	};
> +
>  	pmu {
>  		compatible = "arm,cortex-a7-pmu";
>  		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
> @@ -231,9 +262,75 @@ intc: interrupt-controller@f9000000 {
>  			#interrupt-cells = <3>;
>  		};
>  
> -		apcs: syscon@f9011000 {
> -			compatible = "syscon";
> +		apcs: mailbox@f9011000 {
> +			compatible = "qcom,msm8226-apcs-kpss-global",
> +				     "qcom,msm8916-apcs-kpss-global", "syscon";
>  			reg = <0xf9011000 0x1000>;
> +			#mbox-cells = <1>;
> +			clocks = <&a7pll>, <&gcc GPLL0_VOTE>;
> +			clock-names = "pll", "aux";
> +			#clock-cells = <0>;
> +		};
> +
> +		a7pll: clock@f9016000 {
> +			compatible = "qcom,msm8226-a7pll";
> +			reg = <0xf9016000 0x40>;
> +			#clock-cells = <0>;
> +			clocks = <&xo_board>;
> +			clock-names = "xo";
> +			operating-points-v2 = <&a7pll_opp_table>;
> +
> +			a7pll_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-768000000 {
> +					opp-hz = /bits/ 64 <768000000>;
> +				};

Looks like scaling this PLL should also scale some voltage domains:
CPR (fed by pm8226_s2) and MX

Perhaps hook up MX to this one for now and add CPR to the CPU nodes( & OPP table)
after that is brought up

Konrad