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Mon, 30 Mar 2026 01:16:56 -0700 (PDT) X-Received: by 2002:a17:902:c40e:b0:2ae:826f:2c50 with SMTP id d9443c01a7336-2b0cdc3ab90mr128223005ad.12.1774858616016; Mon, 30 Mar 2026 01:16:56 -0700 (PDT) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b2427c5339sm73986605ad.79.2026.03.30.01.16.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Mar 2026 01:16:55 -0700 (PDT) Message-ID: <6e843004-62ec-46e2-a7c7-5e0ad18d4954@oss.qualcomm.com> Date: Mon, 30 Mar 2026 13:46:49 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/3] PCI: qcom: Program T_POWER_ON To: Shawn Lin , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Jingoo Han Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com, quic_vbadigan@quicinc.com References: <20260311-t_power_on_fux-v3-0-9b1f1d09c6f3@oss.qualcomm.com> <20260311-t_power_on_fux-v3-3-9b1f1d09c6f3@oss.qualcomm.com> <04fdfe0b-5867-0a94-75ec-44cec913756d@rock-chips.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <04fdfe0b-5867-0a94-75ec-44cec913756d@rock-chips.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=I8dohdgg c=1 sm=1 tr=0 ts=69ca3179 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=HIfOsU49naKVPb5QdBEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: ny5MowNropKtcCbI7BhcznYP7wdg1sz2 X-Proofpoint-ORIG-GUID: ny5MowNropKtcCbI7BhcznYP7wdg1sz2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzMwMDA2NCBTYWx0ZWRfX7AHO1dSQiEz8 52bB1IOhVwsHo02hyhVhA+LORIGJ9/ba+1rWrBTzxKf6QEuR/w7Gr4+XLNVbYMZ4guG9G1Bq53E CPHigKteOOcDtcFQCROGYbdldf27X4Xz6qS2LSlUHzTu+cRARMqhOBhenlaTnyDuuHC5lWULeVl XMMYw+AdIymIKzKXzvf5dJLMIz8+shB+wrr/cclw9C6rZmCFWExJRZtCNgfVRrEBQIHBYxLmLtc oo6NVV+hFbrzJtbihhiapWdWzU5GGR9DZBWytJGdSwjBeLZm+oBy6JehFBe6s746WtVgX1iwN+a 1fBgPqoaUA+TZjDEBuakTnq6jIrrwcIR8/tz/eI1vUZIh0/yOJTnus2cfglso1jgcFIiTuLhZmi KB4S4pmDyYruAuknULVg12UtuC+e+LlWIr2wFyL0EeX5CpfAiCcfNfjMZ7HcKGdc+6gn9EawMYB QAsf43b1qmmRfEOHCGg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-29_05,2026-03-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 spamscore=0 adultscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603300064 On 3/13/2026 8:19 AM, Shawn Lin wrote: > 在 2026/03/11 星期三 20:40, Krishna Chaitanya Chundru 写道: >> Some platforms have incorrect T_POWER_ON value programmed in hardware. >> Generally these will be corrected by bootloaders, but not all targets >> support bootloaders to program correct values due to that >> LTR_L1.2_THRESHOLD value calculated by aspm driver can be wrong, which >> can result in improper L1.2 exit behavior and if AER happens to be >> supported and enabled, the error may be *reported* via AER. >> >> Parse "t-power-on-us" property from each root port node and program them >> as part of host initialization using dw_pcie_program_t_power_on() before >> link training. >> >> This property in added to the dtschema here[1]. >> >> Signed-off-by: Krishna Chaitanya Chundru >> >> Link[1]: >> https://lore.kernel.org/all/20260205093346.667898-1-krishna.chundru@oss.qualcomm.com/ >> --- >>   drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ >>   1 file changed, 13 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c >> b/drivers/pci/controller/dwc/pcie-qcom.c >> index >> 67a16af69ddc75fca1b123e70715e692a91a9135..63d5628e988d3c07f42099c0d86e6b80fd54ce32 >> 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -269,6 +269,7 @@ struct qcom_pcie_perst { >>   struct qcom_pcie_port { >>       struct list_head list; >>       struct phy *phy; >> +    u32 l1ss_t_power_on; > > u16? > >>       struct list_head perst; >>   }; >>   @@ -1283,6 +1284,14 @@ static int qcom_pcie_phy_power_on(struct >> qcom_pcie *pcie) >>       return 0; >>   } >>   +static void qcom_pcie_configure_ports(struct qcom_pcie *pcie) >> +{ >> +    struct qcom_pcie_port *port; >> + >> +    list_for_each_entry(port, &pcie->ports, list) >> +        dw_pcie_program_t_power_on(pcie->pci, port->l1ss_t_power_on); >> +} >> + >>   static int qcom_pcie_host_init(struct dw_pcie_rp *pp) >>   { >>       struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >> @@ -1317,6 +1326,8 @@ static int qcom_pcie_host_init(struct >> dw_pcie_rp *pp) >>       dw_pcie_remove_capability(pcie->pci, PCI_CAP_ID_MSIX); >>       dw_pcie_remove_ext_capability(pcie->pci, PCI_EXT_CAP_ID_DPC); >>   +    qcom_pcie_configure_ports(pcie); >> + >>       qcom_pcie_perst_deassert(pcie); >>         if (pcie->cfg->ops->config_sid) { >> @@ -1759,6 +1770,8 @@ static int qcom_pcie_parse_port(struct >> qcom_pcie *pcie, struct device_node *node >>       if (ret) >>           return ret; >>   +    of_property_read_u32(node, "t-power-on-us", >> &port->l1ss_t_power_on); > > Ditto? the property has -us and doesn't have $ref to indicate if it is u32 or u16, by default it is u32 property only. can we can't keep it as u16 even if have always less than u16. - Krishna Chaitanya. >> + >>       port->phy = phy; >>       INIT_LIST_HEAD(&port->list); >>       list_add_tail(&port->list, &pcie->ports); >>