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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-61500ae2f31sm3003928a12.51.2025.07.28.02.25.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Jul 2025 02:25:02 -0700 (PDT) Message-ID: <6e8bcafc-da00-424a-81a3-439e7ed6e080@oss.qualcomm.com> Date: Mon, 28 Jul 2025 11:24:59 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] dt-bindings: clock: qcom: Add SM8750 GPU clocks To: Krzysztof Kozlowski , Konrad Dybcio Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250723-topic-8750_gpucc-v2-0-56c93b84c390@oss.qualcomm.com> <20250723-topic-8750_gpucc-v2-1-56c93b84c390@oss.qualcomm.com> <20250724-blazing-therapeutic-python-1e96ca@kuoka> <7d444f4c-fa1f-4436-b93a-f2d2b6d49de2@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: eWZG340iaxic9iD1l8v1zRHXb0tdScx4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA2NyBTYWx0ZWRfX10xBYMBU0Gba UT9BbPZaMot8TADYcZJzpJyEt+y8rQJg8kN9s/WAMh1cEt41nk/NoeD6eEIndJtPDWmZsnAUyVM arUQOx5m9u9OTsJ0M4WdvFHHiilFK3Ey9jbtml03kGuTDzt8yQ1jNzO/MIro/sNJsT0PaiPygcN JDe+j2v0Iqa0XdKXcU2fRUXJiYjPYBLF1QiHchjaRuDNZYSlGQIPkhJSf9q7P+JWhZUj8F4B6Y7 6/g2EDCMP+ZoefiEgIe+XVawkSRv8humGdFnXozBPCIUNBmAD7zwNY6zPd/s1OLpatozMhNNWmB WdRPDryDPnJBBy7yCFrhYqwJPz0gOiGnr/dQI9pOIqWu7tuLuwSRwnsrei/+3ib7h5D4vl//dSz zN3EEdYnn4JsIGhmBtzHqIHWUOs9gz3hcYYywBm2w7LPgxNs8gYqoP9iLS5uYmfwr/bWfPs2 X-Proofpoint-GUID: eWZG340iaxic9iD1l8v1zRHXb0tdScx4 X-Authority-Analysis: v=2.4 cv=KtNN2XWN c=1 sm=1 tr=0 ts=688741f0 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=Rh5PIcw8VRhVldmlYEYA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 suspectscore=0 adultscore=0 mlxlogscore=999 bulkscore=0 spamscore=0 impostorscore=0 mlxscore=0 malwarescore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507280067 On 7/28/25 7:05 AM, Krzysztof Kozlowski wrote: > On 25/07/2025 11:23, Konrad Dybcio wrote: >> On 7/24/25 4:42 PM, Krzysztof Kozlowski wrote: >>> On 24/07/2025 12:53, Konrad Dybcio wrote: >>>> On 7/24/25 10:18 AM, Krzysztof Kozlowski wrote: >>>>> On Wed, Jul 23, 2025 at 10:38:48PM +0200, Konrad Dybcio wrote: >>>>>> From: Konrad Dybcio >>>>>> >>>>>> The SM8750 features a "traditional" GPU_CC block, much of which is >>>>>> controlled through the GMU microcontroller. Additionally, there's >>>>>> an separate GX_CC block, where the GX GDSC is moved. >>>>>> >>>>>> Add bindings to accommodate for that. >>>>>> >>>>>> Signed-off-by: Konrad Dybcio >>>>>> --- >> >> [...] >> >>> Yes, qcom,gcc. If that was missing intentionally, it is fine assuming >>> you implement the rest of comments. >> >> With the description addition that you suggested above, should I keep >> this file in clocks/ after all? > > Good point, I don't know, this is unusual case. The question is whether > there could be user of this binding/DTS, which would need/use > clock-cells? If none of possible users could use it as a clock > controller, I think it is not a clock controller from how SW sees it. > IOW, it does not matter what it is fully (in bigger picture) if it > cannot be used in that way. > > If all users of the binding can use it only as power domain provided, I > would move it to power with rest of power domains. Also rename the node > name to power-controller or power-domain. The hardware block can be accessed from the CPU directly, skipping the microcontroller (although that is undesirable and the only "real" use for it I can think about is someone trying to get rid of a blob). I can add clock/reset-cells to describe the hardware accurately, but the Linux driver(s - this is a block that exists on many >=2024 SoCs as you may imagine) will continue to only provide a single power domain. With that, I think clock/ makes sense, as this is essentially the same hardware template as other instances of QCOM_*CC Konrad