From: maobibo <maobibo@loongson.cn>
To: "Sergei Shtylyov" <sergei.shtylyov@cogentembedded.com>,
"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"Andrew Morton" <akpm@linux-foundation.org>,
"Paul Burton" <paulburton@kernel.org>,
"Dmitry Korotin" <dkorotin@wavecomp.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Stafford Horne" <shorne@gmail.com>,
"Steven Price" <steven.price@arm.com>,
"Anshuman Khandual" <anshuman.khandual@arm.com>,
"Mike Rapoport" <rppt@linux.ibm.com>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] MIPS: update tlb even if pte entry has no change
Date: Thu, 14 May 2020 19:41:56 +0800 [thread overview]
Message-ID: <6ea926de-042b-eb44-0e41-156e2bd64bd8@loongson.cn> (raw)
In-Reply-To: <f165deac-1a71-dd88-dfe5-c1701f31567b@cogentembedded.com>
On 05/14/2020 05:37 PM, Sergei Shtylyov wrote:
> On 14.05.2020 12:35, Sergei Shtylyov wrote:
>
>>> From: bibo mao <maobibo@loongson.cn>
>>>
>>> If there are two threads reading the same memory and tlb miss happens,
>>> one thread fills pte entry, the other reads new pte value during page fault
>>> handling. PTE value may be updated before page faul, so the process need
>>
>> Fault.
>
> And "needs".
>
>>> need update tlb still.
>
> Oh, and one "need" is enough. :-)
Thank for reviewing my patch, will fix this typo issue in next version.
Best Regards
bibo, mao
>
>>> Also this patch define flush_tlb_fix_spurious_fault as empty, since it not
>>> necessary to flush the page for all CPUs
>>>
>>> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
>> [...]
>
> MBR, Sergei
next prev parent reply other threads:[~2020-05-14 11:42 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-14 2:17 Bibo Mao
2020-05-14 9:33 ` Mike Rapoport
2020-05-14 11:40 ` maobibo
2020-05-14 9:35 ` Sergei Shtylyov
2020-05-14 9:37 ` Sergei Shtylyov
2020-05-14 11:41 ` maobibo [this message]
2020-05-14 13:34 ` Maciej W. Rozycki
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