From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DC48C4167B for ; Thu, 14 Dec 2023 05:44:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1443206AbjLNFo3 (ORCPT ); Thu, 14 Dec 2023 00:44:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1443193AbjLNFo0 (ORCPT ); Thu, 14 Dec 2023 00:44:26 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 195D410A; Wed, 13 Dec 2023 21:44:29 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3BE5iJTW036923; Wed, 13 Dec 2023 23:44:19 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1702532659; bh=5kcNwlTyEanZdUHbBRgU6blj9PGlRg0qWtcJ4LxQqsM=; h=Date:CC:Subject:To:References:From:In-Reply-To; b=CG2uohMNvWz4M39s8NjgVAsGrJ/v0EhEoTrsUt5p5c+Ymy1jWdtm0EKnfvKBbpNMP KcuTjf19n4ryK7C2pYJeiM65TYh+vlwiotjfmP2WXyEF9/Wfyt54gIfIH8jtyu0SPz Jwd2PEhPqbEW2uyDyjw6XtyGw0Slw6hDQ35x1GIQ= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3BE5iJXH100306 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 13 Dec 2023 23:44:19 -0600 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 13 Dec 2023 23:44:18 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 13 Dec 2023 23:44:19 -0600 Received: from [172.24.227.9] (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3BE5iE9x080888; Wed, 13 Dec 2023 23:44:15 -0600 Message-ID: <6f1c1a59-cec0-46d1-8ecb-a82d9d444ccf@ti.com> Date: Thu, 14 Dec 2023 11:14:13 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird CC: , , , , , , , , , , , Subject: Re: [PATCH v2] arm64: dts: ti: k3-am654-icssg2: Enable PHY interrupts for ICSSG2 Content-Language: en-US To: Nishanth Menon References: <20231213080216.1710730-1-s-vadapalli@ti.com> <20231213123819.tqh3lm2ceir3qjbk@swimmer> From: Siddharth Vadapalli In-Reply-To: <20231213123819.tqh3lm2ceir3qjbk@swimmer> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello Nishanth, On 13/12/23 18:08, Nishanth Menon wrote: > On 13:32-20231213, Siddharth Vadapalli wrote: >> Enable interrupt mode of operation of the DP83867 Ethernet PHY which is >> used by ICSSG2. The DP83867 PHY driver already supports interrupt handling >> for interrupts generated by the PHY. Thus, add the necessary device-tree >> support to enable it. >> >> Since the GPIO1_87 line is muxed with EXT_REFCLK1 and SYNC1_OUT, update >> the pinmux to select GPIO1_87 for routing the interrupt. >> >> As the same interrupt line and therefore the same pinmux configuration is >> applicable to both Ethernet PHYs used by ICSSG2, allocate the pinmux >> resource to the first Ethernet PHY alone. ... > > https://www.ti.com/lit/ds/symlink/dp83867ir.pdf -> it looks like the > interrupt pin is level event. but drivers/gpio/gpio-davinci.c:: > gpio_irq_type() -> The SoC cannot handle level, only edge. > > A bit confused here.. GPIO 87 is shared between two phys. isn't it a > case of race? > > PHY1 assets low > phy1 handler starts, but before the driver it clears the condition: > PHY2 asserts low - but since the signal is already low, there is no > pulse > phy1 handler clears phy1 condition, but signal is still low due to phy2? > now phy2 OR phy1 never gets handled since there is never a pulse event > ever again. Yes, you are right! Edge-Triggered interrupts shouldn't be shared. I missed noticing this. Thank you for pointing it out. Since the SoC only supports Edge-Triggered interrupts, I believe that the correct decision would be to use the interrupt for only one of the two PHYs, while leaving the other PHY in polled mode of operation which is the default. Kindly let me know if this is acceptable and I shall update this patch accordingly. > > >> ti,rx-internal-delay = ; >> ti,fifo-depth = ; >> }; >> -- >> 2.34.1 >> > -- Regards, Siddharth.