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Mon, 07 Jul 2025 04:22:31 -0700 (PDT) Message-ID: <6f55d9ba-02c5-4075-a751-018b1521ddd4@linaro.org> Date: Mon, 7 Jul 2025 12:22:30 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] perf: arm_spe: Add barrier before enabling profiling buffer To: Leo Yan Cc: Will Deacon , Mark Rutland , Catalin Marinas , Alexandru Elisei , Anshuman Khandual , Rob Herring , Suzuki Poulose , Robin Murphy , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250701-james-spe-vm-interface-v1-0-52a2cd223d00@linaro.org> <20250701-james-spe-vm-interface-v1-1-52a2cd223d00@linaro.org> <20250704140443.GH1039028@e132581.arm.com> Content-Language: en-US From: James Clark In-Reply-To: <20250704140443.GH1039028@e132581.arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 04/07/2025 3:04 pm, Leo Yan wrote: > On Tue, Jul 01, 2025 at 04:31:57PM +0100, James Clark wrote: >> DEN0154 states that PMBPTR_EL1 must not be modified while the profiling >> buffer is enabled. Ensure that enabling the buffer comes after setting >> PMBPTR_EL1 by inserting an isb(). >> >> This only applies to guests for now, but in future versions of the >> architecture the PE will be allowed to behave in the same way. >> >> Fixes: d5d9696b0380 ("drivers/perf: Add support for ARMv8.2 Statistical Profiling Extension") >> Signed-off-by: James Clark >> --- >> drivers/perf/arm_spe_pmu.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c >> index 3efed8839a4e..6235ca7ecd48 100644 >> --- a/drivers/perf/arm_spe_pmu.c >> +++ b/drivers/perf/arm_spe_pmu.c >> @@ -537,6 +537,7 @@ static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handle, >> limit += (u64)buf->base; >> base = (u64)buf->base + PERF_IDX2OFF(handle->head, buf); >> write_sysreg_s(base, SYS_PMBPTR_EL1); >> + isb(); > > I know that you and Alexandru have discussed whether the isb() should > be placed here or after the out_write_limit label. I should have engaged > in the discussion earlier. Sorry for raising the question now. > > My understanding is that isb() is not only for synchronizing the write > to PMBPTR_EL1. It also serves as a context synchronization event > between any other SPE register writes and the write to > SYS_PMBLIMITR_EL1. > > Let me give an example (perhaps a rare one): if we use perf snapshot > mode or the AUX pause/resume mode, it's possible that the flow does > not trigger an interrupt via overflow. Instead, the sequence might > look like this: > > arm_spe_pmu_stop() > `> arm_spe_pmu_start() > `> arm_spe_perf_aux_output_begin() > > In this case, to ensure that all SPE system registers are properly > written to the hardware, the safest approach is to always execute isb() > just before writing to SYS_PMBLIMITR_EL1. (In other words, after the > label out_write_limit). > > Thanks, > Leo > I think the point is that any write that enables the buffer must come last, but not necessarily all writes. And not all paths in arm_spe_perf_aux_output_begin() enable it so the isb() was only added on the path that does. I couldn't see an issue with your example, are you saying arm_spe_pmu_stop() could call arm_spe_pmu_start()? It doesn't call it directly. Or do you mean the aux pause/resume thing can cause a arm_spe_pmu_start() from any point in time? If that was true then it doesn't matter where the isb() is because you can never be sure it will be before the write. James >> out_write_limit: >> write_sysreg_s(limit, SYS_PMBLIMITR_EL1); >> >> -- >> 2.34.1 >> >> >