From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D362C433E0 for ; Wed, 1 Jul 2020 00:54:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 012B92073E for ; Wed, 1 Jul 2020 00:54:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726122AbgGAAyU (ORCPT ); Tue, 30 Jun 2020 20:54:20 -0400 Received: from mga03.intel.com ([134.134.136.65]:13341 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725805AbgGAAyU (ORCPT ); Tue, 30 Jun 2020 20:54:20 -0400 IronPort-SDR: ALUpbUwX1+ZikdeC9aRma2f1LL83X5kc495q9xQzdgNwz4kYewkgEilCMo9Tm4UcSjrlBppOeb ypYXyCx+pb/Q== X-IronPort-AV: E=McAfee;i="6000,8403,9668"; a="146414767" X-IronPort-AV: E=Sophos;i="5.75,298,1589266800"; d="scan'208";a="146414767" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2020 17:54:19 -0700 IronPort-SDR: lxdO2gwQ0hxRmZ5FMUgXgjzJmAIMg/Sl/33jeqf4837+a10qCDdxgA7DzeGZGpSFhaga22pYzn Vx4F3D6tYfBA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,298,1589266800"; d="scan'208";a="265258365" Received: from allen-box.sh.intel.com (HELO [10.239.159.139]) ([10.239.159.139]) by fmsmga007.fm.intel.com with ESMTP; 30 Jun 2020 17:54:17 -0700 Cc: baolu.lu@linux.intel.com, Yi Liu , "Tian, Kevin" , Raj Ashok , Eric Auger Subject: Re: [PATCH v2 3/7] iommu/vt-d: Fix PASID devTLB invalidation To: Jacob Pan , iommu@lists.linux-foundation.org, LKML , Joerg Roedel , David Woodhouse References: <1593551258-39854-1-git-send-email-jacob.jun.pan@linux.intel.com> <1593551258-39854-4-git-send-email-jacob.jun.pan@linux.intel.com> From: Lu Baolu Message-ID: <6f970f1f-621e-f66e-79d4-f2871c121baa@linux.intel.com> Date: Wed, 1 Jul 2020 08:49:54 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <1593551258-39854-4-git-send-email-jacob.jun.pan@linux.intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jacob, On 7/1/20 5:07 AM, Jacob Pan wrote: > DevTLB flush can be used for both DMA request with and without PASIDs. > The former uses PASID#0 (RID2PASID), latter uses non-zero PASID for SVA > usage. > > This patch adds a check for PASID value such that devTLB flush with > PASID is used for SVA case. This is more efficient in that multiple > PASIDs can be used by a single device, when tearing down a PASID entry > we shall flush only the devTLB specific to a PASID. > > Fixes: 6f7db75e1c46 ("iommu/vt-d: Add second level page table") > Signed-off-by: Jacob Pan > --- > drivers/iommu/intel/pasid.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c > index c81f0f17c6ba..70d21209dd04 100644 > --- a/drivers/iommu/intel/pasid.c > +++ b/drivers/iommu/intel/pasid.c > @@ -486,7 +486,16 @@ devtlb_invalidation_with_pasid(struct intel_iommu *iommu, > qdep = info->ats_qdep; > pfsid = info->pfsid; > > - qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 - VTD_PAGE_SHIFT); > + /* > + * When PASID 0 is used, it indicates RID2PASID(DMA request w/o PASID), > + * devTLB flush w/o PASID should be used. For non-zero PASID under > + * SVA usage, device could do DMA with multiple PASIDs. It is more > + * efficient to flush devTLB specific to the PASID. > + */ > + if (pasid == PASID_RID2PASID) > + qi_flush_dev_iotlb_pasid(iommu, sid, pfsid, pasid, qdep, 0, 64 - VTD_PAGE_SHIFT); > + else > + qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 - VTD_PAGE_SHIFT); The if/else logic is reversed. if (pasid == PASID_RID2PASID) qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 - VTD_PAGE_SHIFT); else qi_flush_dev_iotlb_pasid(iommu, sid, pfsid, pasid, qdep, 0, 64 - VTD_PAGE_SHIFT); Best regards, baolu > } > > void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev, >