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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b041f00d4c2sm571868366b.97.2025.09.02.04.47.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Sep 2025 04:47:24 -0700 (PDT) Message-ID: <6f9b7f9d-9ec7-4827-b6d5-51c42b5eb7b9@oss.qualcomm.com> Date: Tue, 2 Sep 2025 13:47:21 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/3] arm64: dts: qcom: sm8450: Add opp-level to indicate PCIe data rates To: Krishna Chaitanya Chundru , Viresh Kumar , Nishanth Menon , Stephen Boyd , "Rafael J. Wysocki" , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Conor Dooley Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org References: <20250819-opp_pcie-v3-0-f8bd7e05ce41@oss.qualcomm.com> <20250819-opp_pcie-v3-2-f8bd7e05ce41@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250819-opp_pcie-v3-2-f8bd7e05ce41@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAzMSBTYWx0ZWRfX6fHW6XDjyn4p nJ/SeVxYvTH9XIG/7Tdm3hPQSYcrJIThQu3C/6mH1t06zZaS7yNGUK+jbr5uL4JPcGa9pg8AL0F FAqHRrHFpAFJUF023eOe9eSaMonZp+VduGG1+TF8RLcMjf0FqAiJijbREc2yw7tLcqHxaILxndC RudBFbxY21D9D3uBEqGDfialg81+T7kEqIdV8OJs+UsopV/Kq+V+iDA9Np71jHF8vKTjF31T+EB yqB0o+JvaT8lYQL5y0PThvPjp++URshHIHFjHiVcIIbd4vgFkvlKUfPxChE+tvj80h6lRiiW9fA sIqUEGxpxqtyxKQKTCbwt1CGpa2JoLoC6GhZCUbDG9/00t4ncOhRaUPyMGX2Pwm8UT7EFPAGlyP f8r0oVzG X-Authority-Analysis: v=2.4 cv=A8xsP7WG c=1 sm=1 tr=0 ts=68b6d94e cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=6pHcnep46kEejBPVP2gA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-ORIG-GUID: RINz6CivysilpxWbLRDN7KMiybrOvIyn X-Proofpoint-GUID: RINz6CivysilpxWbLRDN7KMiybrOvIyn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-02_03,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 impostorscore=0 bulkscore=0 clxscore=1015 suspectscore=0 malwarescore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300031 On 8/19/25 7:34 AM, Krishna Chaitanya Chundru wrote: > Add opp-level to indicate PCIe data rates and also define OPP enteries > for each link width and data rate. Append the opp level to name of the > opp node to indicate both frequency and level. > > Signed-off-by: Krishna Chaitanya Chundru > --- Reviewed-by: Konrad Dybcio Are there any other SoCs affected? Konrad