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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b97f13ed066sm168825366b.4.2026.03.18.02.29.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Mar 2026 02:29:36 -0700 (PDT) Message-ID: <6fa41a5d-ae11-471c-bc7b-3fd445a01b03@oss.qualcomm.com> Date: Wed, 18 Mar 2026 10:29:34 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 17/27] drm/msm/mdss: use new helper to set amsbc To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20260312-ubwc-rework-v3-0-b7e8f800176a@oss.qualcomm.com> <20260312-ubwc-rework-v3-17-b7e8f800176a@oss.qualcomm.com> <19b36a86-12c7-4710-8f80-5e27c9c00e3c@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=T4+BjvKQ c=1 sm=1 tr=0 ts=69ba7083 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=li3VWkI-OtAmqmHzrUUA:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE4MDA3OSBTYWx0ZWRfX7HfX8ZOZRaXe 37YGYShVudAyuy59tfvCkkA9higYjLcr2M/pEDrKWUk1Ix89lHkA/gGuvsmUM2Hj7at7uSvB3QM wh4rCLUzH3HcqSYfZI+orZDnm/p5Y1JPHHqAil8BuAK2JElstgI5k4t/kqoy/awmHGsJCZsDWk9 N7YMUi9bwxzyQosGBuoRNaIBX6UnLKObt8ShddzoNHeXKn4ZCMcuy1Wjou7mTY804103eFwDkm0 Z/SCOVkRfywyoa19a6KOKuFqZ2xnuWoxq+TN8Gu7Nu+RPcfd01YTxGR3gaG7Pxwyurw1drXDu6c 1ZokXyL/fJ85hfk3bHxPG8gaRg6RgC7RmWgfLcOAnAuWK4Bxila7Kh/SCQw9Md2QKwbDbbzg98B XqFHVjM7ryc7LcvgpbnEC2RNv7zKxKzz9dT3i+kDBKiQcdPOiXVR+DVFYDgc84nj5C/zOUHLcHi 0pB+kg0HCqvKovMIxaQ== X-Proofpoint-GUID: f27Lo1M-9xUcc8ynRzIKREpL8EUoBTDS X-Proofpoint-ORIG-GUID: f27Lo1M-9xUcc8ynRzIKREpL8EUoBTDS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-17_05,2026-03-17_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 phishscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603180079 On 3/16/26 3:20 PM, Dmitry Baryshkov wrote: > On Mon, Mar 16, 2026 at 04:04:46PM +0200, Dmitry Baryshkov wrote: >> On Mon, Mar 16, 2026 at 11:08:00AM +0100, Konrad Dybcio wrote: >>> On 3/13/26 3:26 PM, Dmitry Baryshkov wrote: >>>> On Fri, Mar 13, 2026 at 11:19:59AM +0100, Konrad Dybcio wrote: >>>>> On 3/12/26 2:29 PM, Dmitry Baryshkov wrote: >>>>>> Use freshly defined helper instead of checking the UBWC version >>>>>> directly. >>>>>> >>>>>> Signed-off-by: Dmitry Baryshkov >>>>>> --- >>>>>> drivers/gpu/drm/msm/msm_mdss.c | 2 +- >>>>>> 1 file changed, 1 insertion(+), 1 deletion(-) >>>>>> >>>>>> diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c >>>>>> index ca59bcdde7b2..04efc29f38cd 100644 >>>>>> --- a/drivers/gpu/drm/msm/msm_mdss.c >>>>>> +++ b/drivers/gpu/drm/msm/msm_mdss.c >>>>>> @@ -188,7 +188,7 @@ static void msm_mdss_5x_setup_ubwc(struct msm_mdss *msm_mdss) >>>>>> if (qcom_ubwc_macrotile_mode(data)) >>>>>> value |= MDSS_UBWC_STATIC_MACROTILE_MODE; >>>>>> >>>>>> - if (data->ubwc_enc_version == UBWC_3_0) >>>>>> + if (qcom_ubwc_enable_amsbc(data)) >>>>>> value |= MDSS_UBWC_STATIC_UBWC_AMSBC; >>>>> >>>>> I know it's already there, but fwiw downstream doesn't seem to be >>>>> concerned with toggling AMSBC in MDSS (perhaps incorrectly?) >>>> >>>> Downstream enables it only for the cases where encoder and decoder >>>> use exactly UBWC 3.0. This is not completely correct as the bit doesn't >>>> exist for MDSS 6.x+. For 5.x this is equivalent to the code from the >>>> patch: enable AMSBC if targeting UBWC >= 3.0 (because MDSS 5.x don't >>>> support UBWC 4.0 or higher). >>> >>> Right, this seems to indeed be the case >>> >>> While trying to confirm that, I noticed that some lower-end MDSS 5.x >>> chips (like Talos) report UBWC3 in the register, but the MDSS docs say >>> they're UBWC2 - any idea? >> >> I don't see a complete pixel format document for Talos, but my guess is >> that one of the blocks (GPU, Venus or Camera) doesn't support UBWC 3.0 >> pixel formats. MDSS is just one piece of picture and unfortunately we >> need to use format which is supported by all the blocks. > > And after cross-checking the docs, it is really interesting. It really > looks like for those chips we have used the older core for UBWC, but the > registeres were not updated. One more reason not to trust those and to > use the database instead. Yeah, downstream seems to have passed: qcom,sde-ubwc-version = <0x200>; as well Konrad